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WDT0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected

Registers

LOAD

STAT

CCNT

CTL

RESTART


LOAD

Load Value
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LOAD LOAD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Load Value
bits : 0 - 15 (16 bit)
access : read-write


STAT

Status
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STAT STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQ CLRIRQ LOADING COUNTING LOCKED

IRQ : WDT Interrupt
bits : 0 - 0 (1 bit)
access : read-only

CLRIRQ : Clear Interrupt Register Write Sync in Progress
bits : 1 - 1 (1 bit)
access : read-only

LOADING : Load Register Write Sync in Progress
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

0 : LOAD_MATCH

APB and WDT clock domains LOAD values match.

1 : LOAD_SYNCING

APB LOAD value is being synchronized to WDT clock domain.

End of enumeration elements list.

COUNTING : Control Register Write Sync in Progress
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

0 : COUNT_MATCH

APB and WDT clock domain CTRL values match

1 : COUNT_SYNCING

APB CTRL register values are being synchronized to WDT clock domain.

End of enumeration elements list.

LOCKED : Lock Status Bit
bits : 4 - 4 (1 bit)
access : read-only


CCNT

Current Count Value
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCNT CCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Current Count Value
bits : 0 - 15 (16 bit)
access : read-only


CTL

Control
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQ PRE EN MODE SPARE

IRQ : Timer Interrupt
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : RST

WDT asserts reset when timed out

1 : INT

WDT generates interrupt when timed out

End of enumeration elements list.

PRE : Prescaler
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

0 : div1

Source clock/1

1 : div16

Source clock/16

2 : div256

Source clock/256 (default)

End of enumeration elements list.

EN : Timer Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : WDT_DIS

WDT not enabled

1 : WDT_EN

WDT enabled

End of enumeration elements list.

MODE : Timer Mode
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : FREE_RUN

Free running mode

1 : PERIODIC

Periodic mode

End of enumeration elements list.

SPARE : Unused Spare Bit
bits : 7 - 7 (1 bit)
access : read-write


RESTART

Clear Interrupt
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESTART RESTART read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRWORD

CLRWORD : Clear Watchdog
bits : 0 - 15 (16 bit)
access : write-only



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