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I2C0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection : not protected

Registers

MCTL

MRXCNT

MCRXCNT

ADDR1

ADDR2

BYT

DIV

SCTL

SSTAT

SRX

STX

ALT

ID0

MSTAT

ID1

ID2

ID3

STAT

SHCTL

TCTL

ASTRETCH_SCL

MRX

MTX


MCTL

Master Control
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCTL MCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MASEN COMPLETE LOOPBACK STRETCHSCL IENMRX IENMTX IENALOST IENACK IENCMP MXMITDEC MRXDMA MTXDMA BUSCLR STOPBUSCLR

MASEN : Master Enable
bits : 0 - 0 (1 bit)
access : read-write

COMPLETE : Start Back-off Disable
bits : 1 - 1 (1 bit)
access : read-write

LOOPBACK : Internal Loopback Enable
bits : 2 - 2 (1 bit)
access : read-write

STRETCHSCL : Stretch SCL Enable
bits : 3 - 3 (1 bit)
access : read-write

IENMRX : Receive Request Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write

IENMTX : Transmit Request Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write

IENALOST : Arbitration Lost Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write

IENACK : ACK Not Received Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write

IENCMP : Transaction Completed (or Stop Detected) Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write

MXMITDEC : Decrement Master Tx FIFO Status When a Byte Txed
bits : 9 - 9 (1 bit)
access : read-write

MRXDMA : Enable Master Rx DMA Request
bits : 10 - 10 (1 bit)
access : write-only

MTXDMA : Enable Master Tx DMA Request
bits : 11 - 11 (1 bit)
access : write-only

BUSCLR : Bus-Clear Enable
bits : 12 - 12 (1 bit)
access : read-write

STOPBUSCLR : Prestop Bus Clear
bits : 13 - 13 (1 bit)
access : read-write


MRXCNT

Master Receive Data Count
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MRXCNT MRXCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE EXTEND

VALUE : Receive Count
bits : 0 - 7 (8 bit)
access : read-write

EXTEND : Extended Read
bits : 8 - 8 (1 bit)
access : read-write


MCRXCNT

Master Current Receive Data Count
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCRXCNT MCRXCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Current Receive Count
bits : 0 - 7 (8 bit)
access : read-only


ADDR1

Master Address Byte 1
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADDR1 ADDR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Address Byte 1
bits : 0 - 7 (8 bit)
access : read-write


ADDR2

Master Address Byte 2
address_offset : 0x1C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADDR2 ADDR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Address Byte 2
bits : 0 - 7 (8 bit)
access : read-write


BYT

Start Byte
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BYT BYT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SBYTE

SBYTE : Start Byte
bits : 0 - 7 (8 bit)
access : read-write


DIV

Serial Clock Period Divisor
address_offset : 0x24 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIV DIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOW HIGH

LOW : Serial Clock Low Time
bits : 0 - 7 (8 bit)
access : read-write

HIGH : Serial Clock High Time
bits : 8 - 15 (8 bit)
access : read-write


SCTL

Slave Control
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCTL SCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLVEN ADR10EN GCEN HGCEN GCSBCLR EARLYTXR NACK IENSTOP IENSRX IENSTX STXDEC IENREPST SRXDMA STXDMA

SLVEN : Slave Enable
bits : 0 - 0 (1 bit)
access : read-write

ADR10EN : Enabled 10-bit Addressing
bits : 1 - 1 (1 bit)
access : read-write

GCEN : General Call Enable
bits : 2 - 2 (1 bit)
access : read-write

HGCEN : Hardware General Call Enable
bits : 3 - 3 (1 bit)
access : read-write

GCSBCLR : General Call Status Bit Clear
bits : 4 - 4 (1 bit)
access : write-only

EARLYTXR : Early Transmit Request Mode
bits : 5 - 5 (1 bit)
access : read-write

NACK : NACK Next Communication
bits : 7 - 7 (1 bit)
access : read-write

IENSTOP : Stop Condition Detected Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write

IENSRX : Slave Receive Request Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-write

IENSTX : Slave Transmit Request Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-write

STXDEC : Decrement Slave Tx FIFO Status When a Byte is Txed
bits : 11 - 11 (1 bit)
access : read-write

IENREPST : Repeated Start Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-write

SRXDMA : Enable Slave Rx DMA Request
bits : 13 - 13 (1 bit)
access : read-write

STXDMA : Enable Slave Tx DMA Request
bits : 14 - 14 (1 bit)
access : read-write


SSTAT

Slave I2C Status/Error/IRQ
address_offset : 0x2C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSTAT SSTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STXFSEREQ STXUNDR STXREQ SRXREQ SRXOVR NOACK SBUSY GCINT GCID STOP IDMAT REPSTART START

STXFSEREQ : Slave Tx FIFO Status or Early Request
bits : 0 - 0 (1 bit)
access : read-write

STXUNDR : Slave Transmit FIFO Underflow
bits : 1 - 1 (1 bit)
access : read-only

STXREQ : Slave Transmit Request/Slave Transmit Interrupt
bits : 2 - 2 (1 bit)
access : read-only

SRXREQ : Slave Receive Request
bits : 3 - 3 (1 bit)
access : read-only

SRXOVR : Slave Receive FIFO Overflow
bits : 4 - 4 (1 bit)
access : read-only

NOACK : ACK Not Generated by the Slave
bits : 5 - 5 (1 bit)
access : read-only

SBUSY : Slave Busy
bits : 6 - 6 (1 bit)
access : read-only

GCINT : General Call Interrupt
bits : 7 - 7 (1 bit)
access : read-only

GCID : General ID
bits : 8 - 9 (2 bit)
access : read-only

STOP : Stop After Start and Matching Address
bits : 10 - 10 (1 bit)
access : read-only

IDMAT : Device ID Matched
bits : 11 - 12 (2 bit)
access : read-only

REPSTART : Repeated Start and Matching Address
bits : 13 - 13 (1 bit)
access : read-only

START : Start and Matching Address
bits : 14 - 14 (1 bit)
access : read-only


SRX

Slave Receive
address_offset : 0x30 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRX SRX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Slave Receive Register
bits : 0 - 7 (8 bit)
access : read-only


STX

Slave Transmit
address_offset : 0x34 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STX STX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Slave Transmit Register
bits : 0 - 7 (8 bit)
access : read-write


ALT

Hardware General Call ID
address_offset : 0x38 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ALT ALT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID

ID : Slave Alt
bits : 0 - 7 (8 bit)
access : read-write


ID0

First Slave Address Device ID
address_offset : 0x3C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ID0 ID0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Slave Device ID 0
bits : 0 - 7 (8 bit)
access : read-write


MSTAT

Master Status
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MSTAT MSTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MTXF MTXREQ MRXREQ NACKADDR ALOST MBUSY NACKDATA TCOMP MRXOVR LINEBUSY MSTOP MTXUNDR SDAFILT SCLFILT

MTXF : Master Transmit FIFO Status
bits : 0 - 1 (2 bit)
access : read-only

Enumeration:

0 : FIFO_EMPTY

FIFO Empty.

2 : FIFO_1BYTE

1 byte in FIFO.

3 : FIFO_FULL

FIFO Full.

End of enumeration elements list.

MTXREQ : Master Transmit Request/Clear Master Transmit Interrupt
bits : 2 - 2 (1 bit)
access : read-write

MRXREQ : Master Receive Request
bits : 3 - 3 (1 bit)
access : read-only

NACKADDR : ACK Not Received in Response to an Address
bits : 4 - 4 (1 bit)
access : read-only

ALOST : Arbitration Lost
bits : 5 - 5 (1 bit)
access : read-only

MBUSY : Master Busy
bits : 6 - 6 (1 bit)
access : read-only

NACKDATA : ACK Not Received in Response to Data Write
bits : 7 - 7 (1 bit)
access : read-only

TCOMP : Transaction Complete or Stop Detected
bits : 8 - 8 (1 bit)
access : read-only

MRXOVR : Master Receive FIFO Overflow
bits : 9 - 9 (1 bit)
access : read-only

LINEBUSY : Line is Busy
bits : 10 - 10 (1 bit)
access : read-only

MSTOP : STOP Driven by This I2C Master
bits : 11 - 11 (1 bit)
access : read-only

MTXUNDR : Master Transmit Underflow
bits : 12 - 12 (1 bit)
access : read-only

SDAFILT : State of SDA Line
bits : 13 - 13 (1 bit)
access : read-only

SCLFILT : State of SCL Line
bits : 14 - 14 (1 bit)
access : read-only


ID1

Second Slave Address Device ID
address_offset : 0x40 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ID1 ID1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Slave Device ID 1
bits : 0 - 7 (8 bit)
access : read-write


ID2

Third Slave Address Device ID
address_offset : 0x44 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ID2 ID2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Slave Device ID 2
bits : 0 - 7 (8 bit)
access : read-write


ID3

Fourth Slave Address Device ID
address_offset : 0x48 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ID3 ID3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Slave Device ID 3
bits : 0 - 7 (8 bit)
access : read-write


STAT

Master and Slave FIFO Status
address_offset : 0x4C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STAT STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STXF SRXF MTXF MRXF SFLUSH MFLUSH

STXF : Slave Transmit FIFO Status
bits : 0 - 1 (2 bit)
access : read-only

SRXF : Slave Receive FIFO Status
bits : 2 - 3 (2 bit)
access : read-only

MTXF : Master Transmit FIFO Status
bits : 4 - 5 (2 bit)
access : read-only

MRXF : Master Receive FIFO Status
bits : 6 - 7 (2 bit)
access : read-only

SFLUSH : Flush the Slave Transmit FIFO
bits : 8 - 8 (1 bit)
access : write-only

MFLUSH : Flush the Master Transmit FIFO
bits : 9 - 9 (1 bit)
access : write-only


SHCTL

Shared Control
address_offset : 0x50 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHCTL SHCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RST

RST : Reset START STOP Detect Circuit
bits : 0 - 0 (1 bit)
access : write-only


TCTL

Timing Control Register
address_offset : 0x54 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCTL TCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 THDATIN FILTEROFF

THDATIN : Data in Hold Start
bits : 0 - 4 (5 bit)
access : read-write

FILTEROFF : Input Filter Control
bits : 8 - 8 (1 bit)
access : read-write


ASTRETCH_SCL

Automatic Stretch SCL
address_offset : 0x58 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASTRETCH_SCL ASTRETCH_SCL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MST SLV MSTTMO SLVTMO

MST : Master Automatic Stretch Mode
bits : 0 - 3 (4 bit)
access : read-write

SLV : Slave Automatic Stretch Mode
bits : 4 - 7 (4 bit)
access : read-write

MSTTMO : Master Automatic Stretch Timeout
bits : 8 - 8 (1 bit)
access : read-only

SLVTMO : Slave Automatic Stretch Timeout
bits : 9 - 9 (1 bit)
access : read-only


MRX

Master Receive Data
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MRX MRX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Master Receive Register
bits : 0 - 7 (8 bit)
access : read-only


MTX

Master Transmit Data
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MTX MTX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Master Transmit Register
bits : 0 - 7 (8 bit)
access : read-write



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