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SPI0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected

Registers

STAT

CTL

IEN

CNT

DMA

FIFO_STAT

RD_CTL

FLOW_CTL

WAIT_TMR

CS_CTL

CS_OVERRIDE

RX

TX

DIV


STAT

Status
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STAT STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQ XFRDONE TXEMPTY TXDONE TXUNDR TXIRQ RXIRQ RXOVR CS CSERR CSRISE CSFALL RDY

IRQ : SPI Interrupt Status
bits : 0 - 0 (1 bit)
access : read-only

XFRDONE : SPI Transfer Completion
bits : 1 - 1 (1 bit)
access : read-only

TXEMPTY : SPI Tx FIFO Empty Interrupt
bits : 2 - 2 (1 bit)
access : read-only

TXDONE : SPI Tx Done in Read Command Mode
bits : 3 - 3 (1 bit)
access : read-only

TXUNDR : SPI Tx FIFO Underflow
bits : 4 - 4 (1 bit)
access : read-only

TXIRQ : SPI Tx IRQ
bits : 5 - 5 (1 bit)
access : read-only

RXIRQ : SPI Rx IRQ
bits : 6 - 6 (1 bit)
access : read-only

RXOVR : SPI Rx FIFO Overflow
bits : 7 - 7 (1 bit)
access : read-only

CS : CS Status
bits : 11 - 11 (1 bit)
access : read-only

CSERR : Detected a CS Error Condition in Slave Mode
bits : 12 - 12 (1 bit)
access : read-only

CSRISE : Detected a Rising Edge on CS, in Slave CON Mode
bits : 13 - 13 (1 bit)
access : read-only

CSFALL : Detected a Falling Edge on CS, in Slave CON Mode
bits : 14 - 14 (1 bit)
access : read-only

RDY : Detected an Edge on Ready Indicator for Flow Control
bits : 15 - 15 (1 bit)
access : read-only


CTL

SPI Configuration
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPIEN MASEN CPHA CPOL WOM LSB TIM ZEN RXOF OEN LOOPBACK CON RFLUSH TFLUSH CSRST

SPIEN : SPI Enable
bits : 0 - 0 (1 bit)
access : read-write

MASEN : Master Mode Enable
bits : 1 - 1 (1 bit)
access : read-write

CPHA : Serial Clock Phase Mode
bits : 2 - 2 (1 bit)
access : read-write

CPOL : Serial Clock Polarity
bits : 3 - 3 (1 bit)
access : read-write

WOM : SPI Wired-OR Mode
bits : 4 - 4 (1 bit)
access : read-write

LSB : LSB First Transfer Enable
bits : 5 - 5 (1 bit)
access : read-write

TIM : SPI Transfer and Interrupt Mode
bits : 6 - 6 (1 bit)
access : read-write

ZEN : Transmit Zeros Enable
bits : 7 - 7 (1 bit)
access : read-write

RXOF : Rx Overflow Overwrite Enable
bits : 8 - 8 (1 bit)
access : read-write

OEN : Slave MISO Output Enable
bits : 9 - 9 (1 bit)
access : read-write

LOOPBACK : Loopback Enable
bits : 10 - 10 (1 bit)
access : read-write

CON : Continuous Transfer Enable
bits : 11 - 11 (1 bit)
access : read-write

RFLUSH : SPI Rx FIFO Flush Enable
bits : 12 - 12 (1 bit)
access : read-write

TFLUSH : SPI Tx FIFO Flush Enable
bits : 13 - 13 (1 bit)
access : read-write

CSRST : Reset Mode for CS Error Bit
bits : 14 - 14 (1 bit)
access : read-write


IEN

SPI Interrupts Enable
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IEN IEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQMODE CS TXUNDR RXOVR RDY TXDONE XFRDONE TXEMPTY

IRQMODE : SPI IRQ Mode Bits
bits : 0 - 2 (3 bit)
access : read-write

CS : Enable Interrupt on Every CS Edge in Slave CON Mode
bits : 8 - 8 (1 bit)
access : read-write

TXUNDR : Tx Underflow Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-write

RXOVR : Rx Overflow Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-write

RDY : Ready Signal Edge Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-write

TXDONE : SPI Transmit Done Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-write

XFRDONE : SPI Transfer Completion Interrupt Enable
bits : 13 - 13 (1 bit)
access : read-write

TXEMPTY : Tx FIFO Empty Interrupt Enable
bits : 14 - 14 (1 bit)
access : read-write


CNT

Transfer Byte Count
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNT CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE FRAMECONT

VALUE : Transfer Byte Count
bits : 0 - 13 (14 bit)
access : read-write

FRAMECONT : Continue Frame
bits : 15 - 15 (1 bit)
access : read-write


DMA

SPI DMA Enable
address_offset : 0x1C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA DMA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN TXEN RXEN

EN : Enable DMA for Data Transfer
bits : 0 - 0 (1 bit)
access : read-write

TXEN : Enable Transmit DMA Request
bits : 1 - 1 (1 bit)
access : read-write

RXEN : Enable Receive DMA Request
bits : 2 - 2 (1 bit)
access : read-write


FIFO_STAT

FIFO Status
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO_STAT FIFO_STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TX RX

TX : SPI Tx FIFO Status
bits : 0 - 3 (4 bit)
access : read-only

RX : SPI Rx FIFO Status
bits : 8 - 11 (4 bit)
access : read-only


RD_CTL

Read Control
address_offset : 0x24 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RD_CTL RD_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMDEN OVERLAP TXBYTES THREEPIN

CMDEN : Read Command Enable
bits : 0 - 0 (1 bit)
access : read-write

OVERLAP : Tx/Rx Overlap Mode
bits : 1 - 1 (1 bit)
access : read-write

TXBYTES : Transmit Byte Count - 1 (Read Command)
bits : 2 - 5 (4 bit)
access : read-write

THREEPIN : Three Pin SPI Mode
bits : 8 - 8 (1 bit)
access : read-write


FLOW_CTL

Flow Control
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FLOW_CTL FLOW_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE RDYPOL RDBURSTSZ

MODE : Flow Control Mode
bits : 0 - 1 (2 bit)
access : read-write

RDYPOL : Polarity of RDY/MISO Line
bits : 4 - 4 (1 bit)
access : read-write

RDBURSTSZ : Read Data Burst Size - 1
bits : 6 - 15 (10 bit)
access : read-write


WAIT_TMR

Wait Timer for Flow Control
address_offset : 0x2C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WAIT_TMR WAIT_TMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Wait Timer
bits : 0 - 15 (16 bit)
access : read-write


CS_CTL

Chip Select Control for Multi-slave Connections
address_offset : 0x30 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CS_CTL CS_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL

SEL : Chip Select Control
bits : 0 - 3 (4 bit)
access : read-write


CS_OVERRIDE

Chip Select Override
address_offset : 0x34 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CS_OVERRIDE CS_OVERRIDE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTL

CTL : CS Override Control
bits : 0 - 1 (2 bit)
access : read-write


RX

Receive
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RX RX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BYTE1 BYTE2

BYTE1 : 8-bit Receive Buffer
bits : 0 - 7 (8 bit)
access : read-only

BYTE2 : 8-bit Receive Buffer, Used Only in DMA Modes
bits : 8 - 15 (8 bit)
access : read-only


TX

Transmit
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TX TX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BYTE1 BYTE2

BYTE1 : 8-bit Transmit Buffer
bits : 0 - 7 (8 bit)
access : write-only

BYTE2 : 8-bit Transmit Buffer, Used Only in DMA Modes
bits : 8 - 15 (8 bit)
access : write-only


DIV

SPI Baud Rate Selection
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIV DIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : SPI Clock Divider
bits : 0 - 5 (6 bit)
access : read-write



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