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UART0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected

Registers

RX

TX

MCR

LSR

MSR

SCR

FCR

FBR

DIV

LCR2

CTL

RFC

TFC

RSC

IEN

ACR

ASRL

ASRH

IIR

LCR


RX

Receive Buffer Register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RX RX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RBR

RBR : Receive Buffer Register
bits : 0 - 7 (8 bit)
access : read-only


TX

Transmit Holding Register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : RX
reset_Mask : 0x0

TX TX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 THR

THR : Transmit Holding Register
bits : 0 - 7 (8 bit)
access : write-only


MCR

Modem Control
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCR MCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTR RTS OUT1 OUT2 LOOPBACK

DTR : Data Terminal Ready
bits : 0 - 0 (1 bit)
access : read-write

RTS : Request to Send
bits : 1 - 1 (1 bit)
access : read-write

OUT1 : Output 1
bits : 2 - 2 (1 bit)
access : read-write

OUT2 : Output 2
bits : 3 - 3 (1 bit)
access : read-write

LOOPBACK : Loopback Mode
bits : 4 - 4 (1 bit)
access : read-write


LSR

Line Status
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LSR LSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DR OE PE FE BI THRE TEMT FIFOERR

DR : Data Ready
bits : 0 - 0 (1 bit)
access : read-only

OE : Overrun Error
bits : 1 - 1 (1 bit)
access : read-only

PE : Parity Error
bits : 2 - 2 (1 bit)
access : read-only

FE : Framing Error
bits : 3 - 3 (1 bit)
access : read-only

BI : Break Indicator
bits : 4 - 4 (1 bit)
access : read-only

THRE : Transmit Register Empty
bits : 5 - 5 (1 bit)
access : read-only

TEMT : Transmit and Shift Register Empty Status
bits : 6 - 6 (1 bit)
access : read-only

FIFOERR : Rx FIFO Parity Error/Frame Error/Break Indication
bits : 7 - 7 (1 bit)
access : read-only


MSR

Modem Status
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MSR MSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCTS DDSR TERI DDCD CTS DSR RI DCD

DCTS : Delta CTS
bits : 0 - 0 (1 bit)
access : read-only

DDSR : Delta DSR
bits : 1 - 1 (1 bit)
access : read-only

TERI : Trailing Edge RI
bits : 2 - 2 (1 bit)
access : read-only

DDCD : Delta DCD
bits : 3 - 3 (1 bit)
access : read-only

CTS : Clear to Send
bits : 4 - 4 (1 bit)
access : read-only

DSR : Data Set Ready
bits : 5 - 5 (1 bit)
access : read-only

RI : Ring Indicator
bits : 6 - 6 (1 bit)
access : read-only

DCD : Data Carrier Detect
bits : 7 - 7 (1 bit)
access : read-only


SCR

Scratch Buffer
address_offset : 0x1C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCR SCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCR

SCR : Scratch
bits : 0 - 7 (8 bit)
access : read-write


FCR

FIFO Control
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FCR FCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIFOEN RFCLR TFCLR FDMAMD RFTRIG

FIFOEN : FIFO Enable as to Work in 16550 Mode
bits : 0 - 0 (1 bit)
access : read-write

RFCLR : Clear Rx FIFO
bits : 1 - 1 (1 bit)
access : write-only

TFCLR : Clear Tx FIFO
bits : 2 - 2 (1 bit)
access : write-only

FDMAMD : FIFO DMA Mode
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : MODE0

In DMA mode 0, RX DMA request will be asserted whenever there's data in RBR or RX FIFO and de-assert whenever RBR or RX FIFO is empty TX DMA request will be asserted whenever THR or TX FIFO is empty and de-assert whenever data written to.

1 : MODE1

in DMA mode 1, RX DMA request will be asserted whenever RX FIFO trig level or time out reached and de-assert thereafter when RX FIFO is empty TX DMA request will be asserted whenever TX FIFO is empty and de-assert thereafter when TX FIFO is completely filled up full.

End of enumeration elements list.

RFTRIG : Rx FIFO Trigger Level
bits : 6 - 7 (2 bit)
access : read-write


FBR

Fractional Baud Rate
address_offset : 0x24 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FBR FBR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIVN DIVM FBEN

DIVN : Fractional Baud Rate N Divide Bits 0 to 2047
bits : 0 - 10 (11 bit)
access : read-write

DIVM : Fractional Baud Rate M Divide Bits 1 to 3
bits : 11 - 12 (2 bit)
access : read-write

FBEN : Fractional Baud Rate Generator Enable
bits : 15 - 15 (1 bit)
access : read-write


DIV

Baud Rate Divider
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIV DIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV

DIV : Baud Rate Divider
bits : 0 - 15 (16 bit)
access : read-write


LCR2

Second Line Control
address_offset : 0x2C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LCR2 LCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OSR

OSR : Over Sample Rate
bits : 0 - 1 (2 bit)
access : read-write


CTL

UART Control Register
address_offset : 0x30 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FORCECLK RXINV REV

FORCECLK : Force UCLK on
bits : 1 - 1 (1 bit)
access : read-write

RXINV : Invert Receiver Line
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : NOTINV_RX

Don't invert receiver line (idling high).

1 : INV_RX

Invert receiver line (idling low).

End of enumeration elements list.

REV : UART Revision ID
bits : 8 - 15 (8 bit)
access : read-only


RFC

RX FIFO Byte Count
address_offset : 0x34 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RFC RFC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFC

RFC : Current Rx FIFO Data Bytes
bits : 0 - 4 (5 bit)
access : read-only


TFC

TX FIFO Byte Count
address_offset : 0x38 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TFC TFC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TFC

TFC : Current Tx FIFO Data Bytes
bits : 0 - 4 (5 bit)
access : read-only


RSC

RS485 Half-duplex Control
address_offset : 0x3C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSC RSC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OENP OENSP DISRX DISTX

OENP : SOUT_EN Polarity
bits : 0 - 0 (1 bit)
access : read-write

OENSP : SOUT_EN De-assert Before Full Stop Bit(s)
bits : 1 - 1 (1 bit)
access : read-write

DISRX : Disable Rx When Transmitting
bits : 2 - 2 (1 bit)
access : read-write

DISTX : Hold off Tx When Receiving
bits : 3 - 3 (1 bit)
access : read-write


IEN

Interrupt Enable
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IEN IEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERBFI ETBEI ELSI EDSSI EDMAT EDMAR

ERBFI : Receive Buffer Full Interrupt
bits : 0 - 0 (1 bit)
access : read-write

ETBEI : Transmit Buffer Empty Interrupt
bits : 1 - 1 (1 bit)
access : read-write

ELSI : Rx Status Interrupt
bits : 2 - 2 (1 bit)
access : read-write

EDSSI : Modem Status Interrupt
bits : 3 - 3 (1 bit)
access : read-write

EDMAT : DMA Requests in Transmit Mode
bits : 4 - 4 (1 bit)
access : read-write

EDMAR : DMA Requests in Receive Mode
bits : 5 - 5 (1 bit)
access : read-write


ACR

Auto Baud Control
address_offset : 0x40 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACR ACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ABE DNIEN TOIEN SEC EEC

ABE : Auto Baud Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DIS_AUTOBAUD

Disable auto baudrate

1 : EN_AUTOBAUD

Enable auto baudrate

End of enumeration elements list.

DNIEN : Enable Done Interrupt
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : DIS_DONEINT

Disable done interrupt

1 : EN_DONEINT

Enable done interrupt

End of enumeration elements list.

TOIEN : Enable Time-out Interrupt
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DIS_TIMEOUTINT

Disable timeout interrupt

1 : EN_TIMEOUTINT

Enable timeout interrupt

End of enumeration elements list.

SEC : Starting Edge Count
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

0 : SEC_EDGE1

First edge

1 : SEC_EDGE2

Second edge

2 : SEC_EDGE3

Third edge

3 : SEC_EDGE4

Fourth edge

4 : SEC_EDGE5

Fifth edge

5 : SEC_EDGE6

Sixth edge

6 : SEC_EDGE7

Seventh edge

7 : SEC_EDGE8

Eighth edge

End of enumeration elements list.

EEC : Ending Edge Count
bits : 8 - 11 (4 bit)
access : read-write

Enumeration:

0 : EEC_EDGE1

First edge

1 : EEC_EDGE2

Second edge

2 : EEC_EDGE3

Third edge

3 : EEC_EDGE4

Fourth edge

4 : EEC_EDGE5

Fifth edge

5 : EEC_EDGE6

Sixth edge

6 : EEC_EDGE7

Seventh edge

7 : EEC_EDGE8

Eighth edge

8 : EEC_EDGE9

Ninth edge

End of enumeration elements list.


ASRL

Auto Baud Status (Low)
address_offset : 0x44 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASRL ASRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DONE BRKTO NSETO NEETO CNT

DONE : Auto Baud Done Successfully
bits : 0 - 0 (1 bit)
access : read-only

BRKTO : Timed Out Due to Long Time Break Condition
bits : 1 - 1 (1 bit)
access : read-only

NSETO : Timed Out Due to No Valid Start Edge Found
bits : 2 - 2 (1 bit)
access : read-only

NEETO : Timed Out Due to No Valid Ending Edge Found
bits : 3 - 3 (1 bit)
access : read-only

CNT : CNT[11:0] Auto Baud Counter Value
bits : 4 - 15 (12 bit)
access : read-only


ASRH

Auto Baud Status (High)
address_offset : 0x48 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASRH ASRH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : CNT[19:12] Auto Baud Counter Value
bits : 0 - 7 (8 bit)
access : read-only


IIR

Interrupt ID
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IIR IIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NIRQ STAT FEND

NIRQ : Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-only

STAT : Interrupt Status
bits : 1 - 3 (3 bit)
access : read-only

Enumeration:

0 : STAT_EDSSI

Modem status interrupt (Read MSR register to clear)

1 : STAT_ETBEI

Transmit buffer empty interrupt (Write to Tx register or read IIR register to clear)

2 : STAT_ERBFI

Receive buffer full interrupt (Read Rx register to clear)

3 : STAT_RLSI

Receive line status interrupt (Read LSR register to clear)

6 : STAT_RFTOI

Receive FIFO time-out interrupt (Read Rx register to clear)

End of enumeration elements list.

FEND : FIFO Enabled
bits : 6 - 7 (2 bit)
access : read-only


LCR

Line Control
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LCR LCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WLS STOP PEN EPS SP BRK

WLS : Word Length Select
bits : 0 - 1 (2 bit)
access : read-write

STOP : Stop Bit
bits : 2 - 2 (1 bit)
access : read-write

PEN : Parity Enable
bits : 3 - 3 (1 bit)
access : read-write

EPS : Parity Select
bits : 4 - 4 (1 bit)
access : read-write

SP : Stick Parity
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : PAR_NOTFORCED

Parity will not be forced based on Parity Select and Parity Enable bits.

1 : PAR_FORCED

Parity forced based on Parity Select and Parity Enable bits.

End of enumeration elements list.

BRK : Set Break
bits : 6 - 6 (1 bit)
access : read-write



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