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FLCC0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected

Registers

STAT

KH_DATA0

KH_DATA1

PAGE_ADDR0

PAGE_ADDR1

KEY

WR_ABORT_ADDR

WRPROT

SIGNATURE

UCFG

TIME_PARAM0

TIME_PARAM1

ABORT_EN_LO

IEN

ABORT_EN_HI

ECC_CFG

ECC_ADDR

POR_SEC

VOL_CFG

CMD

KH_ADDR


STAT

Status
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STAT STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMDBUSY WRCLOSE CMDCOMP WRALCOMP CMDFAIL SLEEPING ECCERRCMD ECCRDERR OVERLAP SIGNERR INIT ECCINFOSIGN ECCERRCNT ECCICODE ECCDCODE CACHESRAMPERR ACCESS_MODE

CMDBUSY : Command busy
bits : 0 - 0 (1 bit)
access : read-only

WRCLOSE : WRITE registers are closed
bits : 1 - 1 (1 bit)
access : read-only

CMDCOMP : Command complete
bits : 2 - 2 (1 bit)
access : read-only

WRALCOMP : Write almost complete
bits : 3 - 3 (1 bit)
access : read-only

CMDFAIL : Provides information on command failures
bits : 4 - 5 (2 bit)
access : read-only

SLEEPING : Flash array is in low power (sleep) mode
bits : 6 - 6 (1 bit)
access : read-only

ECCERRCMD : ECC errors detected during user issued SIGN command
bits : 7 - 8 (2 bit)
access : read-only

ECCRDERR : ECC IRQ cause
bits : 9 - 10 (2 bit)
access : read-only

OVERLAP : Overlapping Command
bits : 11 - 11 (1 bit)
access : read-write

SIGNERR : Signature check failure during initialization
bits : 13 - 13 (1 bit)
access : read-only

INIT : Flash controller initialization in progress
bits : 14 - 14 (1 bit)
access : read-only

ECCINFOSIGN : ECC status of flash initialization
bits : 15 - 16 (2 bit)
access : read-only

ECCERRCNT : ECC correction counter
bits : 17 - 19 (3 bit)
access : read-only

ECCICODE : ICode AHB Bus Error ECC status
bits : 25 - 26 (2 bit)
access : read-only

ECCDCODE : DCode AHB Bus Error ECC status
bits : 27 - 28 (2 bit)
access : read-only

CACHESRAMPERR : SRAM parity errors in Cache Controller
bits : 29 - 29 (1 bit)
access : read-only

ACCESS_MODE : Access Mode
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : Direct

Flash controller is currently in Direct Access mode user access to all registers is enabled

1 : Indirect

Flash Controller is currently in Indirect Access mode user access to registers is limited to read-only access of the status register. Full register access will be restored when the Cryptographic module releases control of the flash controller (crypto completes the ongoing operation within the protected key storage region)

End of enumeration elements list.


KH_DATA0

Write Lower Data
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

KH_DATA0 KH_DATA0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Lower half of 64-bit dual word data to be written on a Write command
bits : 0 - 31 (32 bit)
access : read-write


KH_DATA1

Write Upper Data
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

KH_DATA1 KH_DATA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Upper half of 64-bit dual word data to be written on a Write command
bits : 0 - 31 (32 bit)
access : read-write


PAGE_ADDR0

Lower Page Address
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PAGE_ADDR0 PAGE_ADDR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Lower address bits of the page address
bits : 10 - 19 (10 bit)
access : read-write


PAGE_ADDR1

Upper Page Address
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PAGE_ADDR1 PAGE_ADDR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Upper address bits of the page address
bits : 10 - 19 (10 bit)
access : read-write


KEY

Key
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

KEY KEY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Key register
bits : 0 - 31 (32 bit)
access : write-only


WR_ABORT_ADDR

Write Abort Address
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WR_ABORT_ADDR WR_ABORT_ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Address of recently aborted write command
bits : 0 - 31 (32 bit)
access : read-only


WRPROT

Write Protection
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WRPROT WRPROT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WORD

WORD : Clear bits to write protect related groups of user space pages
bits : 0 - 31 (32 bit)
access : read-write


SIGNATURE

Signature
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SIGNATURE SIGNATURE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Read signature
bits : 0 - 31 (32 bit)
access : read-only


UCFG

User Configuration
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UCFG UCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KHDMAEN AUTOINCEN

KHDMAEN : Key hole DMA enable
bits : 0 - 0 (1 bit)
access : read-write

AUTOINCEN : Auto Address Increment for Key Hole Access
bits : 1 - 1 (1 bit)
access : read-write


TIME_PARAM0

Time Parameter 0
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIME_PARAM0 TIME_PARAM0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIVREFCLK TNVS TPGS TPROG TNVH TRCV TERASE TNVH1

DIVREFCLK : Divide Reference Clock (by 2)
bits : 0 - 0 (1 bit)
access : read-write

TNVS : PROG/ERASE to NVSTR setup time
bits : 4 - 7 (4 bit)
access : read-write

TPGS : NVSTR to Program setup time
bits : 8 - 11 (4 bit)
access : read-write

TPROG : Program time
bits : 12 - 15 (4 bit)
access : read-write

TNVH : NVSTR Hold time
bits : 16 - 19 (4 bit)
access : read-write

TRCV : Recovery time
bits : 20 - 23 (4 bit)
access : read-write

TERASE : Erase Time
bits : 24 - 27 (4 bit)
access : read-write

TNVH1 : NVSTR Hold time during Mass Erase
bits : 28 - 31 (4 bit)
access : read-write


TIME_PARAM1

Time Parameter 1
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIME_PARAM1 TIME_PARAM1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TWK WAITSTATES CURWAITSTATES

TWK : Wake up time
bits : 0 - 3 (4 bit)
access : read-write

WAITSTATES : Number of wait states to access flash
bits : 4 - 6 (3 bit)
access : read-write

CURWAITSTATES : Current wait states [2:0]
bits : 8 - 10 (3 bit)
access : read-only


ABORT_EN_LO

IRQ Abort Enable (Lower Bits)
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ABORT_EN_LO ABORT_EN_LO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : VALUE[31:0] Sys IRQ Abort Enable
bits : 0 - 31 (32 bit)
access : read-write


IEN

Interrupt Enable
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IEN IEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMDCMPLT WRALCMPLT CMDFAIL ECC_CORRECT ECC_ERROR

CMDCMPLT : Command complete interrupt enable
bits : 0 - 0 (1 bit)
access : read-write

WRALCMPLT : Write almost complete interrupt enable
bits : 1 - 1 (1 bit)
access : read-write

CMDFAIL : Command fail interrupt enable
bits : 2 - 2 (1 bit)
access : read-write

ECC_CORRECT : Control whether to generate bus errors, interrupts, or neither in response to 1-bit ECC Correction events
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : NONE_cor

Do not generate a response to ECC events

1 : BUS_ERR_cor

Generate Bus Errors in response to ECC events

2 : IRQ_cor

Generate IRQs in response to ECC events

End of enumeration elements list.

ECC_ERROR : Control whether to generate bus errors, interrupts, or neither in response to 2-bit ECC Error events
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

0 : NONE_err

Do not generate a response to ECC events

1 : BUS_ERR_err

Generate Bus Errors in response to ECC events

2 : IRQ_err

Generate IRQs in response to ECC events

End of enumeration elements list.


ABORT_EN_HI

IRQ Abort Enable (Upper Bits)
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ABORT_EN_HI ABORT_EN_HI read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : VALUE[63:32] Sys IRQ Abort Enable
bits : 0 - 31 (32 bit)
access : read-write


ECC_CFG

ECC Configuration
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ECC_CFG ECC_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN INFOEN PTR

EN : ECC Enable
bits : 0 - 0 (1 bit)
access : read-write

INFOEN : Info space ECC Enable bit
bits : 1 - 1 (1 bit)
access : read-write

PTR : ECC start page pointer
bits : 8 - 31 (24 bit)
access : read-write


ECC_ADDR

ECC Status (Address)
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ECC_ADDR ECC_ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : This register has the address for which ECC error is detected
bits : 0 - 19 (20 bit)
access : read-only


POR_SEC

Flash Security
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POR_SEC POR_SEC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SECURE

SECURE : Set this bit to prevent read or write access to User Space (sticky when set)
bits : 0 - 0 (1 bit)
access : read-write


VOL_CFG

Volatile Flash Configuration
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VOL_CFG VOL_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INFO_REMAP

INFO_REMAP : Alias the info space to the base address of user space
bits : 0 - 0 (1 bit)
access : read-write


CMD

Command
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMD CMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Commands
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0 : IDLE

IDLE

1 : ABORT

ABORT

2 : SLEEP

Requests flash to enter Sleep mode

3 : SIGN

SIGN

4 : WRITE

WRITE

5 : BLANK_CHECK

Checks all of User Space fails if any bits in user space are cleared

6 : ERASEPAGE

ERASEPAGE

7 : MASSERASE

MASSERASE

End of enumeration elements list.


KH_ADDR

Write Address
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

KH_ADDR KH_ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Address to be written on a WRITE command
bits : 3 - 19 (17 bit)
access : read-write



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