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SPORT0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTL_A

NUMTRAN_A

CNVT_A

TX_A

RX_A

DIV_A

CTL_B

DIV_B

IEN_B

STAT_B

NUMTRAN_B

CNVT_B

TX_B

RX_B

IEN_A

STAT_A


CTL_A

Half SPORT 'A' Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL_A CTL_A read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPEN FSMUXSEL CKMUXSEL LSBF SLEN ICLK OPMODE CKRE FSR IFS DIFS LFS LAFS PACK FSERRMODE GCLKEN DATMUXSEL SPTRAN DMAEN

SPEN : Serial Port Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : CTL_DIS

Disable

1 : CTL_EN

Enable

End of enumeration elements list.

FSMUXSEL : Frame Sync Multiplexer Select
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : CTL_FS_MUX_DIS

Disable frame sync multiplexing

1 : CTL_FS_MUX_EN

Enable frame sync multiplexing

End of enumeration elements list.

CKMUXSEL : Clock Multiplexer Select
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : CTL_CLK_MUX_DIS

Disable serial clock multiplexing

1 : CTL_CLK_MUX_EN

Enable serial clock multiplexing

End of enumeration elements list.

LSBF : Least-Significant Bit First
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : CTL_MSB_FIRST

MSB first sent/received

1 : CTL_LSB_FIRST

LSB first sent/received

End of enumeration elements list.

SLEN : Serial Word Length
bits : 4 - 8 (5 bit)
access : read-write

ICLK : Internal Clock
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : CTL_EXTERNAL_CLK

External clock

1 : CTL_INTERNAL_CLK

Internal clock

End of enumeration elements list.

OPMODE : Operation mode
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : CTL_SERIAL

DSP standard

1 : CTL_TIMER_EN_MODE

Timer_enable mode

End of enumeration elements list.

CKRE : Clock Rising Edge
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : CTL_CLK_FALL_EDGE

Clock falling edge

1 : CTL_CLK_RISE_EDGE

Clock rising edge

End of enumeration elements list.

FSR : Frame Sync Required
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : CTL_FS_NOT_REQ

No frame sync required

1 : CTL_FS_REQ

Frame sync required

End of enumeration elements list.

IFS : Internal Frame Sync
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : CTL_EXTERNAL_FS

External frame sync

1 : CTL_INTERNAL_FS

Internal frame sync

End of enumeration elements list.

DIFS : Data-Independent Frame Sync
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : CTL_DATA_DEP_FS

Data-dependent frame sync

1 : CTL_DATA_INDP_FS

Data-independent frame sync

End of enumeration elements list.

LFS : Active-Low Frame Sync
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : CTL_FS_LO

Active high frame sync

1 : CTL_FS_HI

Active low frame sync

End of enumeration elements list.

LAFS : Late Frame Sync
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : CTL_EARLY_FS

Early frame sync

1 : CTL_LATE_FS

Late frame sync

End of enumeration elements list.

PACK : Packing Enable
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0 : CTL_PACK_DIS

Disable

1 : CTL_PACK_8BIT

8-bit packing enable

2 : CTL_PACK_16BIT

16-bit packing enable

End of enumeration elements list.

FSERRMODE : Frame Sync Error Operation
bits : 20 - 20 (1 bit)
access : read-write

GCLKEN : Gated Clock Enable
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : CTL_GCLK_DIS

Disable

1 : CTL_GCLK_EN

Enable

End of enumeration elements list.

DATMUXSEL : Data Multiplexer select
bits : 22 - 22 (1 bit)
access : read-write

SPTRAN : Serial Port Transfer Direction
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : CTL_RX

Receive

1 : CTL_TX

Transmit

End of enumeration elements list.

DMAEN : DMA Enable
bits : 26 - 26 (1 bit)
access : read-write


NUMTRAN_A

Half SPORT A Number of transfers register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NUMTRAN_A NUMTRAN_A read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Number of transfers (Half SPORT A)
bits : 0 - 11 (12 bit)
access : read-write


CNVT_A

Half SPORT 'A' CNV width
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNVT_A CNVT_A read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WID POL CNVT2FS

WID : CNV signal width: Half SPORT A
bits : 0 - 3 (4 bit)
access : read-write

POL : Polarity of the CNV signal
bits : 8 - 8 (1 bit)
access : read-write

CNVT2FS : CNV to FS duration: Half SPORT A
bits : 16 - 23 (8 bit)
access : read-write


TX_A

Half SPORT 'A' Tx Buffer Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TX_A TX_A read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Transmit Buffer
bits : 0 - 31 (32 bit)
access : write-only


RX_A

Half SPORT 'A' Rx Buffer Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RX_A RX_A read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Receive Buffer
bits : 0 - 31 (32 bit)
access : read-only


DIV_A

Half SPORT 'A' Divisor Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIV_A DIV_A read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKDIV FSDIV

CLKDIV : Clock Divisor
bits : 0 - 15 (16 bit)
access : read-write

FSDIV : Frame Sync Divisor
bits : 16 - 23 (8 bit)
access : read-write


CTL_B

Half SPORT 'B' Control Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL_B CTL_B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPEN LSBF SLEN ICLK OPMODE CKRE FSR IFS DIFS LFS LAFS PACK FSERRMODE GCLKEN SPTRAN DMAEN

SPEN : Serial Port Enable
bits : 0 - 0 (1 bit)
access : read-write

LSBF : Least-Significant Bit First
bits : 3 - 3 (1 bit)
access : read-write

SLEN : Serial Word Length
bits : 4 - 8 (5 bit)
access : read-write

ICLK : Internal Clock
bits : 10 - 10 (1 bit)
access : read-write

OPMODE : Operation mode
bits : 11 - 11 (1 bit)
access : read-write

CKRE : Clock Rising Edge
bits : 12 - 12 (1 bit)
access : read-write

FSR : Frame Sync Required
bits : 13 - 13 (1 bit)
access : read-write

IFS : Internal Frame Sync
bits : 14 - 14 (1 bit)
access : read-write

DIFS : Data-Independent Frame Sync
bits : 15 - 15 (1 bit)
access : read-write

LFS : Active-Low Frame Sync
bits : 16 - 16 (1 bit)
access : read-write

LAFS : Late Frame Sync
bits : 17 - 17 (1 bit)
access : read-write

PACK : Packing Enable
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0 : CTL_PACK_DIS

Disable

1 : CTL_PACK_8BIT

8-bit packing enable

2 : CTL_PACK_16BIT

16-bit packing enable

End of enumeration elements list.

FSERRMODE : Frame Sync Error Operation
bits : 20 - 20 (1 bit)
access : read-write

GCLKEN : Gated Clock Enable
bits : 21 - 21 (1 bit)
access : read-write

SPTRAN : Serial Port Transfer Direction
bits : 25 - 25 (1 bit)
access : read-write

DMAEN : DMA Enable
bits : 26 - 26 (1 bit)
access : read-write


DIV_B

Half SPORT 'B' Divisor Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIV_B DIV_B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKDIV FSDIV

CLKDIV : Clock Divisor
bits : 0 - 15 (16 bit)
access : read-write

FSDIV : Frame Sync Divisor
bits : 16 - 23 (8 bit)
access : read-write


IEN_B

Half SPORT B's Interrupt Enable register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IEN_B IEN_B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TF DERRMSK FSERRMSK DATA SYSDATERR

TF : Transmit Finish Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : CTL_TXFIN_DIS

Transfer Finish Interrupt is disabled

1 : CTL_TXFIN_EN

Transfer Finish Interrupt is Enabled

End of enumeration elements list.

DERRMSK : Data Error (Interrupt) Mask
bits : 1 - 1 (1 bit)
access : read-write

FSERRMSK : Frame Sync Error (Interrupt) Mask
bits : 2 - 2 (1 bit)
access : read-write

DATA : Data request interrupt to the core
bits : 3 - 3 (1 bit)
access : read-write

SYSDATERR : Data error for system writes or reads
bits : 4 - 4 (1 bit)
access : read-write


STAT_B

Half SPORT 'B' Status register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STAT_B STAT_B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TFI DERR FSERR DATA SYSDATERR DXS

TFI : Transmit Finish Interrupt Status
bits : 0 - 0 (1 bit)
access : read-only

DERR : Data Error Status
bits : 1 - 1 (1 bit)
access : read-only

FSERR : Frame Sync Error Status
bits : 2 - 2 (1 bit)
access : read-only

DATA : Data Buffer status
bits : 3 - 3 (1 bit)
access : read-only

SYSDATERR : System Data Error Status
bits : 4 - 4 (1 bit)
access : read-only

DXS : Data Transfer Buffer Status
bits : 8 - 9 (2 bit)
access : read-only

Enumeration:

0 : CTL_EMPTY

Empty

2 : CTL_PART_FULL

Partially full

3 : CTL_FULL

Full

End of enumeration elements list.


NUMTRAN_B

Half SPORT B Number of transfers register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NUMTRAN_B NUMTRAN_B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Number of transfers (Half SPORT B)
bits : 0 - 11 (12 bit)
access : read-write


CNVT_B

Half SPORT 'B' CNV width register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNVT_B CNVT_B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WID POL CNVT2FS

WID : CNV signal width: Half SPORT B
bits : 0 - 3 (4 bit)
access : read-write

POL : Polarity of the CNV signal
bits : 8 - 8 (1 bit)
access : read-write

CNVT2FS : CNV to FS duration: Half SPORT B
bits : 16 - 23 (8 bit)
access : read-write


TX_B

Half SPORT 'B' Tx Buffer Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TX_B TX_B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Transmit Buffer
bits : 0 - 31 (32 bit)
access : write-only


RX_B

Half SPORT 'B' Rx Buffer Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RX_B RX_B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Receive Buffer
bits : 0 - 31 (32 bit)
access : read-only


IEN_A

Half SPORT A's Interrupt Enable register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IEN_A IEN_A read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TF DERRMSK FSERRMSK DATA SYSDATERR

TF : Transfer Finish Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : CTL_TXFIN_DIS

Transfer finish Interrupt is disabled

1 : CTL_TXFIN_EN

Transfer Finish Interrupt is Enabled

End of enumeration elements list.

DERRMSK : Data Error (Interrupt) Mask
bits : 1 - 1 (1 bit)
access : read-write

FSERRMSK : Frame Sync Error (Interrupt) Mask
bits : 2 - 2 (1 bit)
access : read-write

DATA : Data request interrupt to the core
bits : 3 - 3 (1 bit)
access : read-write

SYSDATERR : Data error for system writes or reads
bits : 4 - 4 (1 bit)
access : read-write


STAT_A

Half SPORT 'A' Status register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STAT_A STAT_A read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TFI DERR FSERR DATA SYSDATERR DXS

TFI : Transmit Finish Interrupt Status
bits : 0 - 0 (1 bit)
access : read-only

DERR : Data Error Status
bits : 1 - 1 (1 bit)
access : read-only

FSERR : Frame Sync Error Status
bits : 2 - 2 (1 bit)
access : read-only

DATA : Data Buffer status
bits : 3 - 3 (1 bit)
access : read-only

SYSDATERR : System Data Error Status
bits : 4 - 4 (1 bit)
access : read-only

DXS : Data Transfer Buffer Status
bits : 8 - 9 (2 bit)
access : read-only

Enumeration:

0 : CTL_EMPTY

Empty

2 : CTL_PART_FULL

Partially full

3 : CTL_FULL

Full

End of enumeration elements list.



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