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PMG0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected

Registers

IEN

SHDN_STAT

SRAMRET

TRIM

PSM_STAT

RST_STAT

CTL1

PWRMOD

PWRKEY


IEN

Power Supply Monitor Interrupt Enable
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IEN IEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VBAT VREGUNDR VREGOVR RANGEBAT IENBAT

VBAT : Enable Interrupt for VBAT
bits : 0 - 0 (1 bit)
access : read-write

VREGUNDR : Enable Interrupt When VREG Under Voltage (Below 1V)
bits : 1 - 1 (1 bit)
access : read-write

VREGOVR : Enable Interrupt When VREG Over Voltage (Above 1.32V)
bits : 2 - 2 (1 bit)
access : read-write

RANGEBAT : Battery Monitor Range
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : region1

Configure to generate interrupt if VBAT in Region1

1 : region2

Configure to generate interrupt if VBAT in Region2

2 : region3

Configure to generate interrupt if VBAT in Region3

3 : NA

NA

End of enumeration elements list.

IENBAT : Interrupt Enable for VBAT Range
bits : 10 - 10 (1 bit)
access : read-write


SHDN_STAT

Shutdown Status Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHDN_STAT SHDN_STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTINT0 EXTINT1 EXTINT2 RTC

EXTINT0 : Interrupt from External Interrupt 0
bits : 0 - 0 (1 bit)
access : read-only

EXTINT1 : Interrupt from External Interrupt 1
bits : 1 - 1 (1 bit)
access : read-only

EXTINT2 : Interrupt from External Interrupt 2
bits : 2 - 2 (1 bit)
access : read-only

RTC : Interrupt from RTC
bits : 3 - 3 (1 bit)
access : read-only


SRAMRET

Control for Retention SRAM in Hibernate Mode
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRAMRET SRAMRET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RET1 RET2 RET3 RET4 HIBERNATE_SRAM_LOAD_MODE

RET1 : Enable Retention Bank 1 (12 KB)
bits : 0 - 0 (1 bit)
access : read-write

RET2 : Enable Retention Bank 3 and Bank 4 (32 KB)
bits : 1 - 1 (1 bit)
access : read-write

RET3 : Enable Retention Bank 5 (32 KB)
bits : 8 - 8 (1 bit)
access : read-write

RET4 : Enable Retention Bank 6 and Bank 7 (32 KB)
bits : 9 - 9 (1 bit)
access : read-write

HIBERNATE_SRAM_LOAD_MODE : Hibernate Mode SRAM Load Mode Control
bits : 23 - 23 (1 bit)
access : read-write


TRIM

Trimming Bits
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRIM TRIM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 hibernate_load_mode

hibernate_load_mode : Hibernate Mode Load Mode Control
bits : 29 - 31 (3 bit)
access : read-write

Enumeration:

0 : HIGH_LOAD

High hibernate load

7 : LOW_LOAD

Low hibernate load

End of enumeration elements list.


PSM_STAT

Power Supply Monitor Status
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSM_STAT PSM_STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VBATUNDR VREGUNDR VREGOVR WICENACK RANGE1 RANGE2 RANGE3 RORANGE1 RORANGE2 RORANGE3

VBATUNDR : Status Bit Indicating an Alarm That Battery is Below 1.8V
bits : 0 - 0 (1 bit)
access : read-write

VREGUNDR : Status Bit for Alarm Indicating VREG is Below 1V
bits : 1 - 1 (1 bit)
access : read-write

VREGOVR : Status Bit for Alarm Indicating Over Voltage for VREG
bits : 2 - 2 (1 bit)
access : read-write

WICENACK : WIC Enable Acknowledge from Cortex
bits : 7 - 7 (1 bit)
access : read-only

RANGE1 : VBAT Range1
bits : 8 - 8 (1 bit)
access : read-write

RANGE2 : VBAT Range2
bits : 9 - 9 (1 bit)
access : read-write

RANGE3 : VBAT Range3
bits : 10 - 10 (1 bit)
access : read-write

RORANGE1 : VBAT Range1
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

0 : batstat1

VBAT NOT in the range specified

1 : batstat0

VBAT in the range specified

End of enumeration elements list.

RORANGE2 : VBAT Range2
bits : 14 - 14 (1 bit)
access : read-only

RORANGE3 : VBAT Range3
bits : 15 - 15 (1 bit)
access : read-only


RST_STAT

Reset Status
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RST_STAT RST_STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 POR EXTRST WDRST SWRST PORSRC

POR : Power-on Reset
bits : 0 - 0 (1 bit)
access : read-write

EXTRST : External Reset
bits : 1 - 1 (1 bit)
access : read-write

WDRST : Watchdog Timeout
bits : 2 - 2 (1 bit)
access : read-write

SWRST : Software Reset
bits : 3 - 3 (1 bit)
access : read-write

PORSRC : Power on Reset Source
bits : 4 - 5 (2 bit)
access : read-only

Enumeration:

0 : FAILSAFE_HV

POR triggered because VBAT drops below Fail Safe

1 : RST_VBAT

POR trigger because VBAT supply (VBAT < 1.7 V)

2 : RST_VREG

POR triggered because VDD supply (VDD < 1.08 V)

3 : FAILSAFE_LV

POR triggered because VREG drops below Fail Safe

End of enumeration elements list.


CTL1

HPBUCK Control
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL1 CTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HPBUCKEN HPBUCK_LD_MODE HPBUCK_LOWPWR_MODE

HPBUCKEN : Enable HP Buck
bits : 0 - 0 (1 bit)
access : read-write

HPBUCK_LD_MODE : HP Buck Load Mode
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : HPBUCKLOWLOAD

HPBUCK Low load mode is enabled

1 : HPBUCKHIGHLOAD

HPBUCK High load mode is enabled

End of enumeration elements list.

HPBUCK_LOWPWR_MODE : HP Buck Low Power Mode
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : LOWPWRDisable

HPBUCK Low power mode is disabled

1 : LOWPWREnable

HPBUCK Low power mode is enabled

End of enumeration elements list.


PWRMOD

Power Mode Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWRMOD PWRMOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE MONVBATN

MODE : Power Mode Bits
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : FLEXI

Flexi Mode

2 : HIBERNATE

Hibernate Mode

3 : SHUTDOWN

Shutdown Mode

End of enumeration elements list.

MONVBATN : Monitor VBAT During Hibernate Mode
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : MONITOR_EN

VBAT monitor enabled in PMG block

1 : MONITOR_DIS

VBAT monitor disabled in PMG block

End of enumeration elements list.


PWRKEY

Key Protection for PMG_PWRMOD and PMG_SRAMRET
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWRKEY PWRKEY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Power Control Key
bits : 0 - 15 (16 bit)
access : write-only



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