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PMG0_TST

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected

Registers

SRAM_CTL

SRAM_INITSTAT

CLR_LATCH_GPIOS

SCRPAD_IMG

SCRPAD_3V_RD

FAST_SHT_WAKEUP


SRAM_CTL

Control for SRAM Parity and Instruction SRAM
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRAM_CTL SRAM_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BNK1EN BNK2EN BNK7EN STARTINIT AUTOINIT ABTINIT PENBNK0 PENBNK1 PENBNK2 PENBNK3 PENBNK4 PENBNK5 PENBNK6 PENBNK7 INSTREN

BNK1EN : Enable Initialization
bits : 1 - 1 (1 bit)
access : read-write

BNK2EN : Enable Initialization
bits : 2 - 2 (1 bit)
access : read-write

BNK7EN : Enable Initialization
bits : 7 - 7 (1 bit)
access : read-write

STARTINIT : Start Manual Initialization
bits : 13 - 13 (1 bit)
access : read-write

AUTOINIT : Automatic Initialization on Wake up from Hibernate Mode
bits : 14 - 14 (1 bit)
access : read-write

ABTINIT : Abort Current Initialization. Self-cleared
bits : 15 - 15 (1 bit)
access : read-write

PENBNK0 : Enable Parity Check
bits : 16 - 16 (1 bit)
access : read-write

PENBNK1 : Enable Parity Check
bits : 17 - 17 (1 bit)
access : read-write

PENBNK2 : Enable Parity Check
bits : 18 - 18 (1 bit)
access : read-write

PENBNK3 : Enable Parity Check
bits : 19 - 19 (1 bit)
access : read-write

PENBNK4 : Enable Parity Check
bits : 20 - 20 (1 bit)
access : read-write

PENBNK5 : Enable Parity Check
bits : 21 - 21 (1 bit)
access : read-write

PENBNK6 : Enable Parity Check
bits : 22 - 22 (1 bit)
access : read-write

PENBNK7 : Enable Parity Check
bits : 23 - 23 (1 bit)
access : read-write

INSTREN : Enables 32kB Instruction SRAM
bits : 31 - 31 (1 bit)
access : read-write


SRAM_INITSTAT

Initialization Status Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRAM_INITSTAT SRAM_INITSTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BNK0DONE BNK1DONE BNK2DONE BNK3DONE BNK4DONE BNK5DONE BNK6DONE BNK7DONE

BNK0DONE : Bank 0 Initialization Status
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0 : NO_BANK0_INIT

Bank 0 not initialized

1 : BANK0_INIT

Bank 0 initialized

End of enumeration elements list.

BNK1DONE : Bank 1 Initialization Status
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

0 : NO_BANK1_INIT

Bank 1 not initialized

1 : BANK1_INIT

Bank 1 initialized

End of enumeration elements list.

BNK2DONE : Bank 2 Initialization Status
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

0 : NO_BANK2_INIT

Bank 2 not initialized

1 : BANK2_INIT

Bank 2 initialized

End of enumeration elements list.

BNK3DONE : Bank 3 Initialization Status
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

0 : NO_BANK3_INIT

Bank 3 not initialized

1 : BANK3_INIT

Bank 3 initialized

End of enumeration elements list.

BNK4DONE : Bank 4 Initialization Status
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

0 : NO_BANK4_INIT

Bank 4 not initialized

1 : BANK4_INIT

Bank 4 initialized

End of enumeration elements list.

BNK5DONE : Bank 5 Initialization Status
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

0 : NO_BANK5_INIT

Bank 5 not initialized

1 : BANK5_INIT

Bank 5 initialized

End of enumeration elements list.

BNK6DONE : Bank 6 Initialization Status
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

0 : NO_BANK6_INIT

Bank 6 not initialized

1 : BANK6_INIT

Bank 6 initialized

End of enumeration elements list.

BNK7DONE : Bank 7 Initialization Status
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

0 : NO_BANK7_INIT

Bank 7 not initialized

1 : BANK7_INIT

Bank 7 initialized

End of enumeration elements list.


CLR_LATCH_GPIOS

Clear GPIO After Shutdown Mode
address_offset : 0x68 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLR_LATCH_GPIOS CLR_LATCH_GPIOS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Clear the Latches for GPIOs
bits : 0 - 15 (16 bit)
access : write-only


SCRPAD_IMG

Scratch Pad Image
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCRPAD_IMG SCRPAD_IMG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Scratch Image
bits : 0 - 31 (32 bit)
access : read-write


SCRPAD_3V_RD

Scratch Pad Saved in Battery Domain
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCRPAD_3V_RD SCRPAD_3V_RD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Reading the Scratch Pad Stored in Shutdown Mode
bits : 0 - 31 (32 bit)
access : read-only


FAST_SHT_WAKEUP

Fast Shutdown Wake-up Enable
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FAST_SHT_WAKEUP FAST_SHT_WAKEUP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FAST_SHT_WAKEUP

FAST_SHT_WAKEUP : Enables Fast Shutdown Wake-up
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : FASTWAKE_DIS

Fast shutdown wakeup is disabled

1 : FASTWAKE_EN

Fast shutdown wakeup is enabled

End of enumeration elements list.



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