\n

BUSM0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected

Registers

ARBIT0

ARBIT4

ARBIT1

ARBIT2

ARBIT3


ARBIT0

Arbitration Priority Configuration for FLASH and SRAM0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ARBIT0 ARBIT0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FLSH_DCODE FLSH_SBUS FLSH_DMA0 SRAM0_DCODE SRAM0_SBUS SRAM0_DMA0

FLSH_DCODE : Flash priority for DCODE
bits : 0 - 1 (2 bit)
access : read-write

FLSH_SBUS : Flash priority for SBUS
bits : 2 - 3 (2 bit)
access : read-write

FLSH_DMA0 : Flash priority for DMA0
bits : 4 - 5 (2 bit)
access : read-write

SRAM0_DCODE : SRAM0 priority for Dcode
bits : 16 - 17 (2 bit)
access : read-write

SRAM0_SBUS : SRAM0 priority for SBUS
bits : 18 - 19 (2 bit)
access : read-write

SRAM0_DMA0 : SRAM0 priority for DMA0
bits : 20 - 21 (2 bit)
access : read-write


ARBIT4

Arbitration Priority Configuration for SRAM1 and SIP
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ARBIT4 ARBIT4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRAM2_DCODE SRAM2_SBUS SRAM2_DMA0

SRAM2_DCODE : SRAM2 priority for Dcode
bits : 0 - 1 (2 bit)
access : read-write

SRAM2_SBUS : SRAM2 priority for SBUS
bits : 2 - 3 (2 bit)
access : read-write

SRAM2_DMA0 : SRAM2 priority for DMA0
bits : 4 - 5 (2 bit)
access : read-write


ARBIT1

Arbitration Priority Configuration for SRAM1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ARBIT1 ARBIT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRAM1_DCODE SRAM1_SBUS SRAM1_DMA0

SRAM1_DCODE : SRAM1 priority for Dcode
bits : 0 - 1 (2 bit)
access : read-write

SRAM1_SBUS : SRAM1 priority for SBUS
bits : 2 - 3 (2 bit)
access : read-write

SRAM1_DMA0 : SRAM1 priority for DMA0
bits : 4 - 5 (2 bit)
access : read-write


ARBIT2

Arbitration Priority Configuration for APB32 and APB16
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ARBIT2 ARBIT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 APB32_DCODE APB32_SBUS APB32_DMA0 APB16_DCODE APB16_SBUS APB16_DMA0

APB32_DCODE : APB32 priority for DCODE
bits : 0 - 1 (2 bit)
access : read-write

APB32_SBUS : APB32 priority for SBUS
bits : 2 - 3 (2 bit)
access : read-write

APB32_DMA0 : APB32 priority for DMA0
bits : 4 - 5 (2 bit)
access : read-write

APB16_DCODE : APB16 priority for DCODE
bits : 16 - 17 (2 bit)
access : read-write

APB16_SBUS : APB16 priority for SBUS
bits : 18 - 19 (2 bit)
access : read-write

APB16_DMA0 : APB16 priority for DMA0
bits : 20 - 21 (2 bit)
access : read-write


ARBIT3

Arbitration Priority Configuration for APB16 priority for core and for DMA1
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ARBIT3 ARBIT3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 APB16_CORE APB16_DMA1 APB16_4DMA_CORE APB16_4DMA_DMA1

APB16_CORE : APB16 priority for CORE
bits : 0 - 0 (1 bit)
access : read-write

APB16_DMA1 : APB16 priority for DMA1
bits : 1 - 1 (1 bit)
access : read-write

APB16_4DMA_CORE : APB16 for dma priority for CORE
bits : 16 - 16 (1 bit)
access : read-write

APB16_4DMA_DMA1 : APB16 for dma priority for DMA1
bits : 17 - 17 (1 bit)
access : read-write



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