\n

TIMER

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected

Registers

TMR0_CTRL

TMR0_VALUE

TMR0_RELOAD

TMR0_INT


TMR0_CTRL

Timer 0 Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMR0_CTRL TMR0_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTRL0 CTRL1 CTRL2 CTRL3

CTRL0 : Enable decrement control
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : 0

Disable (Timer stop decrement)

1 : 1

Enable (Timer start decrement)

End of enumeration elements list.

CTRL1 : Select external input as enable
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0 : 0

Disable

1 : 1

Enable (Timer stop when EXTIN=0)

End of enumeration elements list.

CTRL2 : Select external input as clock
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

0 : 0

Disable

1 : 1

Enable (Timer decrement when EXTIN rising edge)

End of enumeration elements list.

CTRL3 : Timer interrupt enable
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

0 : 0

Disable

1 : 1

Enable

End of enumeration elements list.


TMR0_VALUE

Timer 0 Current Value Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMR0_VALUE TMR0_VALUE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TMR0_RELOAD

Timer 0 Reload Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMR0_RELOAD TMR0_RELOAD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TMR0_INT

Timer 0 Interrupt Status Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMR0_INT TMR0_INT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTSTATUS

INTSTATUS : interrupt status (TIMERINT status)
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : 0

Interrupt not occur

1 : 1

Interrupt occur, write 1 to clear INTSTATUS

End of enumeration elements list.



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