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DUALTIMER

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected

Registers

DUALTMR2_LOAD

DUALTMR2_RIS

DUALTMR2_MIS

DUALTMR2_BGLOAD

DUALTMR2_VALUE

DUALTMR2_CTRL

DUALTMR2_INTCLR


DUALTMR2_LOAD

Dual Timer 2 Load register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DUALTMR2_LOAD DUALTMR2_LOAD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DUALTMR2_RIS

Dual Timer 2 Raw Interrupt register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DUALTMR2_RIS DUALTMR2_RIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RIS

RIS : Dual timer Raw interrupt status
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0 : 0

VALUE[31:0] not counts down to 0

1 : 1

VALUE[31:0] had counted down to 0

End of enumeration elements list.


DUALTMR2_MIS

Dual Timer 2 Mask Interrupt register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DUALTMR2_MIS DUALTMR2_MIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MIS

MIS : Dual timer interrupt enabled status from the counter
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0 : 0

INTEN=0 or RIS=0. Dual Timer interrupt not occur

1 : 1

INTEN=1 and RIS=1. Dual Timer interrupt occur

End of enumeration elements list.


DUALTMR2_BGLOAD

Dual Timer 2 Back Ground Load register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DUALTMR2_BGLOAD DUALTMR2_BGLOAD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DUALTMR2_VALUE

Dual Timer 2 current Value register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DUALTMR2_VALUE DUALTMR2_VALUE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DUALTMR2_CTRL

Dual Timer 2 Control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DUALTMR2_CTRL DUALTMR2_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OS SLT PRE INTEN MD EN

OS : Dual timer one-shot count selects
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : 0

Wrapping

1 : 1

One-shot

End of enumeration elements list.

SLT : Dual timer size selects 16-bit or 32-bit counter operation
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0 : 0

16-bit counter

1 : 1

32-bit counter

End of enumeration elements list.

PRE : Dual timer size selects 16-bit or 32-bit counter operation
bits : 2 - 5 (4 bit)
access : read-write

Enumeration:

3 : Dual timer prescale

Undefined

3 : Dual timer prescale

Undefined

3 : Dual timer prescale

Undefined

3 : Dual timer prescale

Undefined

End of enumeration elements list.

INTEN : Dual timer interrupt enable
bits : 5 - 10 (6 bit)
access : read-write

Enumeration:

0 : 0

Dual Timer interrupt disable

1 : 1

Dual Timer interrupt enable

End of enumeration elements list.

MD : Dual timer Mode
bits : 6 - 12 (7 bit)
access : read-write

Enumeration:

0 : 0

Free-running mode

1 : 1

Periodic mode

End of enumeration elements list.

EN : Dual timer x Enable
bits : 7 - 14 (8 bit)
access : read-write

Enumeration:

0 : 0

Disable

1 : 1

Enable (Dual timer start count down)

End of enumeration elements list.


DUALTMR2_INTCLR

Dual Timer 2 Interrupt Clear register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DUALTMR2_INTCLR DUALTMR2_INTCLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTCLR

INTCLR : Timer interrupt clear. Write any value to this register to clean RIS and MIS.
bits : 0 - 0 (1 bit)
access : write-only

Enumeration:

0 : 0

Timer interrupt clear

1 : 1

Timer interrupt clear

End of enumeration elements list.



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