Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected
UART Data Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UART Baud rate divider register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UART Status Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STATE0 : TX buffer full
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : 0
TX buffer not full
1 : 1
TX buffer full
End of enumeration elements list.
STATE1 : RX buffer full
bits : 1 - 2 (2 bit)
access : read-only
Enumeration:
0 : 0
RX buffer not full
1 : 1
RX buffer full
End of enumeration elements list.
STATE2 : TX buffer overrun
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : 0
TX Buffer does not overrun
1 : 1
TX Buffer has overrun. Write 1 to clean this bit
End of enumeration elements list.
STATE3 : RX buffer overrun
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : 0
RX Buffer does not overrun
1 : 1
RX Buffer has overrun. Write 1 to clean this bit
End of enumeration elements list.
UART Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTRL0 : TX enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : 0
Disable UART TX
1 : 1
Enable UART TX
End of enumeration elements list.
CTRL1 : RX enable
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : 0
Disable UART RX
1 : 1
Enable UART RX
End of enumeration elements list.
CTRL2 : TX interrupt enable
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : 0
Disable UART TX interrupt
1 : 1
Enable UART TX interrupt
End of enumeration elements list.
CTRL3 : RX buffer overrun
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : 0
Disable UART RX interrupt
1 : 1
Enable UART RX interrupt
End of enumeration elements list.
CTRL4 : TX overrun interrupt enable
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : 0
Disable UART TX overrun interrupt
1 : 1
Enable UART TX overrun interrupt
End of enumeration elements list.
CTRL5 : RX overrun interrupt enable
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : 0
Disable UART RX overrun interrupt
1 : 1
Enable UART RX overrun interrupt
End of enumeration elements list.
UART interrupt state and clear Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT0 : TX interrupt
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : 0
TX interrupt does not occur
1 : 1
TX interrupt has occurred. Write 1 to clear this bit
End of enumeration elements list.
INT1 : RX interrupt
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : 0
RX interrupt does not occur
1 : 1
RX interrupt has occurred. Write 1 to clear this bit
End of enumeration elements list.
INT2 : TX overrun interrupt
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : 0
TX overrun interrupt does not occur
1 : 1
TX overrun interrupt has occurred. Write 1 to clear this bit
End of enumeration elements list.
INT3 : RX buffer overrun
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : 0
RX overrun interrupt does not occur
1 : 1
RX overrun interrupt has occurred. Write 1 to clear this bit
End of enumeration elements list.
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