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AFIO

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

EVCR

EXTICR3

EXTICR4

MAPR2

MAPR

EXTICR1

EXTICR2


EVCR

Event Control Register (AFIO_EVCR)
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVCR EVCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIN PORT EVOE

PIN : Pin selection
bits : 0 - 3 (4 bit)

PORT : Port selection
bits : 4 - 6 (3 bit)

EVOE : Event Output Enable
bits : 7 - 7 (1 bit)


EXTICR3

External interrupt configuration register 3 (AFIO_EXTICR3)
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTICR3 EXTICR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI8 EXTI9 EXTI10 EXTI11

EXTI8 : EXTI8 configuration
bits : 0 - 3 (4 bit)

EXTI9 : EXTI9 configuration
bits : 4 - 7 (4 bit)

EXTI10 : EXTI10 configuration
bits : 8 - 11 (4 bit)

EXTI11 : EXTI11 configuration
bits : 12 - 15 (4 bit)


EXTICR4

External interrupt configuration register 4 (AFIO_EXTICR4)
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTICR4 EXTICR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI12 EXTI13 EXTI14 EXTI15

EXTI12 : EXTI12 configuration
bits : 0 - 3 (4 bit)

EXTI13 : EXTI13 configuration
bits : 4 - 7 (4 bit)

EXTI14 : EXTI14 configuration
bits : 8 - 11 (4 bit)

EXTI15 : EXTI15 configuration
bits : 12 - 15 (4 bit)


MAPR2

AF remap and debug I/O configuration register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAPR2 MAPR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM9_REMAP TIM10_REMAP TIM11_REMAP TIM13_REMAP TIM14_REMAP FSMC_NADV

TIM9_REMAP : TIM9 remapping
bits : 5 - 5 (1 bit)

TIM10_REMAP : TIM10 remapping
bits : 6 - 6 (1 bit)

TIM11_REMAP : TIM11 remapping
bits : 7 - 7 (1 bit)

TIM13_REMAP : TIM13 remapping
bits : 8 - 8 (1 bit)

TIM14_REMAP : TIM14 remapping
bits : 9 - 9 (1 bit)

FSMC_NADV : NADV connect/disconnect
bits : 10 - 10 (1 bit)


MAPR

AF remap and debug I/O configuration register (AFIO_MAPR)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAPR MAPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPI1_REMAP I2C1_REMAP USART1_REMAP USART2_REMAP USART3_REMAP TIM1_REMAP TIM2_REMAP TIM3_REMAP TIM4_REMAP CAN_REMAP PD01_REMAP TIM5CH4_IREMAP ADC1_ETRGINJ_REMAP ADC1_ETRGREG_REMAP ADC2_ETRGINJ_REMAP ADC2_ETRGREG_REMAP SWJ_CFG

SPI1_REMAP : SPI1 remapping
bits : 0 - 0 (1 bit)
access : read-write

I2C1_REMAP : I2C1 remapping
bits : 1 - 1 (1 bit)
access : read-write

USART1_REMAP : USART1 remapping
bits : 2 - 2 (1 bit)
access : read-write

USART2_REMAP : USART2 remapping
bits : 3 - 3 (1 bit)
access : read-write

USART3_REMAP : USART3 remapping
bits : 4 - 5 (2 bit)
access : read-write

TIM1_REMAP : TIM1 remapping
bits : 6 - 7 (2 bit)
access : read-write

TIM2_REMAP : TIM2 remapping
bits : 8 - 9 (2 bit)
access : read-write

TIM3_REMAP : TIM3 remapping
bits : 10 - 11 (2 bit)
access : read-write

TIM4_REMAP : TIM4 remapping
bits : 12 - 12 (1 bit)
access : read-write

CAN_REMAP : CAN1 remapping
bits : 13 - 14 (2 bit)
access : read-write

PD01_REMAP : Port D0/Port D1 mapping on OSCIN/OSCOUT
bits : 15 - 15 (1 bit)
access : read-write

TIM5CH4_IREMAP : Set and cleared by software
bits : 16 - 16 (1 bit)
access : read-write

ADC1_ETRGINJ_REMAP : ADC 1 External trigger injected conversion remapping
bits : 17 - 17 (1 bit)
access : read-write

ADC1_ETRGREG_REMAP : ADC 1 external trigger regular conversion remapping
bits : 18 - 18 (1 bit)
access : read-write

ADC2_ETRGINJ_REMAP : ADC 2 external trigger injected conversion remapping
bits : 19 - 19 (1 bit)
access : read-write

ADC2_ETRGREG_REMAP : ADC 2 external trigger regular conversion remapping
bits : 20 - 20 (1 bit)
access : read-write

SWJ_CFG : Serial wire JTAG configuration
bits : 24 - 26 (3 bit)
access : write-only


EXTICR1

External interrupt configuration register 1 (AFIO_EXTICR1)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTICR1 EXTICR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI0 EXTI1 EXTI2 EXTI3

EXTI0 : EXTI0 configuration
bits : 0 - 3 (4 bit)

EXTI1 : EXTI1 configuration
bits : 4 - 7 (4 bit)

EXTI2 : EXTI2 configuration
bits : 8 - 11 (4 bit)

EXTI3 : EXTI3 configuration
bits : 12 - 15 (4 bit)


EXTICR2

External interrupt configuration register 2 (AFIO_EXTICR2)
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTICR2 EXTICR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI4 EXTI5 EXTI6 EXTI7

EXTI4 : EXTI4 configuration
bits : 0 - 3 (4 bit)

EXTI5 : EXTI5 configuration
bits : 4 - 7 (4 bit)

EXTI6 : EXTI6 configuration
bits : 8 - 11 (4 bit)

EXTI7 : EXTI7 configuration
bits : 12 - 15 (4 bit)



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