UART

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected

Registers

DATA

BAUDDIV

STATE

CTRL

INTSTATUS

INTCLEAR


DATA

Recieve and Transmit Data Value
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BAUDDIV

Baudrate Divider
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

STATE

UART Status Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXBF RXBF TXOV RXOV

TXBF : TX Buffer Full
bits : 0 - 0
access : read-only

RXBF : RX Buffer Full
bits : 1 - 2
access : read-only

TXOV : TX Buffer Overun (write 1 to clear)
bits : 2 - 4

RXOV : RX Buffer Overun (write 1 to clear)
bits : 3 - 6


CTRL

UART Control Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXEN RXEN TXINT RXINT TXOVINT RVOVINT HSTX

TXEN : TX Enable
bits : 0 - 0

Enumeration:

0 : Disable

Disabled

1 : Enable

Enabled

End of enumeration elements list.

RXEN : RX Enable
bits : 1 - 2

Enumeration:

0 : Disable

Disabled

1 : Enable

Enabled

End of enumeration elements list.

TXINT : TX Interrupt Enable
bits : 2 - 4

Enumeration:

0 : Disable

Disabled

1 : Enable

Enabled

End of enumeration elements list.

RXINT : RX Interrupt Enable
bits : 3 - 6

Enumeration:

0 : Disable

Disabled

1 : Enable

Enabled

End of enumeration elements list.

TXOVINT : TX Overrun Interrupt Enable
bits : 4 - 8

Enumeration:

0 : Disable

Disabled

1 : Enable

Enabled

End of enumeration elements list.

RVOVINT : RX Overrun Interrupt Enable
bits : 5 - 10

Enumeration:

0 : Disable

Disabled

1 : Enable

Enabled

End of enumeration elements list.

HSTX : High Speed Test Mode for TX only
bits : 6 - 12

Enumeration:

0 : Disable

Disabled

1 : Enable

Enabled

End of enumeration elements list.


INTSTATUS

UART Interrupt Status Register
address_offset : 0xC Bytes (0x0)
access : read-only
reset_value : 0x0

read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINT RXINT TXOV RXOV

TXINT : TX interrupt
bits : 0 - 0

RXINT : RX interrupt
bits : 1 - 2

TXOV : TX Overrun interrupt
bits : 2 - 4

RXOV : RX Overrun interrupt
bits : 3 - 6


INTCLEAR

UART Interrupt CLEAR Register
address_offset : 0xC Bytes (0x0)
access : write-only
reset_value : 0x0
alternate_register : INTSTATUS

write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINT RXINT TXOV RXOV

TXINT : TX interrupt
bits : 0 - 0

RXINT : RX interrupt
bits : 1 - 2

TXOV : TX Overrun interrupt
bits : 2 - 4

RXOV : RX Overrun interrupt
bits : 3 - 6



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