Registers
IntStatus
Interrupt Status Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IntErrClr
Interrupt Error Clear Register
address_offset : 0x10 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
C0SrcAddr
Channel Source Address Registers
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
C0DestAddr
Channel Destination Address Registers
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
C0LLI
Channel Linked List Item Register
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
C0Control
Channel Control Registers
address_offset : 0x10C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
C0Configuration
Channel Configuration Registers
address_offset : 0x110 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
C1SrcAddr
Channel Source Address Registers
address_offset : 0x120 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
C1DestAddr
Channel Destination Address Registers
address_offset : 0x124 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
C1LLI
Channel Linked List Item Register
address_offset : 0x128 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
C1Control
Channel Control Registers
address_offset : 0x12C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
C1Configuration
Channel Configuration Registers
address_offset : 0x130 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RawIntTCStatus
Raw Interrupt Terminal Count Status Register
address_offset : 0x14 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RawIntErrorStatus
Raw Error Interrupt Status Register
address_offset : 0x18 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EnbldChns
Enabled Channel Register
address_offset : 0x1C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SoftBReq
Software Burst Request Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SoftSReq
Software Single Request Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SoftLBReq
Software Last Burst Request Register
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SoftLSReq
Software Last Single Request Register
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Configuration
Configuration Register
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Sync
Synchronization Register
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IntTCStatus
Interrupt Terminal Count Status Register
address_offset : 0x4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ITCR
Test Control Register
address_offset : 0x500 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ITOP1
Integration Test Output Register 1
address_offset : 0x504 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ITOP2
Integration Test Output Register 2
address_offset : 0x508 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ITOP3
Integration Test Output Register 3
address_offset : 0x50C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IntTCClear
Interrupt Terminal Count Clear Register
address_offset : 0x8 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
IntErrorStatus
Interrupt Error Status Register
address_offset : 0xC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
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