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SPI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x40 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR0

CPSR

IMSC

RIS

MIS

ICR

DMACR

CR1

DR

SR


CR0

Control register 0
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR0 CR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSS FRF SPO SPH SCR

DSS : Data Size Select
bits : 0 - 3 (4 bit)

FRF : Frame format
bits : 4 - 9 (6 bit)

SPO : SSPCLKOUT polarity
bits : 6 - 12 (7 bit)

SPH : SSPCLKOUT phase
bits : 7 - 14 (8 bit)

SCR : Serial clock rate
bits : 8 - 23 (16 bit)


CPSR

Clock prescale register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPSR CPSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPSDVSR

CPSDVSR : Clock prescale divisor
bits : 0 - 7 (8 bit)


IMSC

Interrupt mask set or clear register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMSC IMSC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RORIM RTIM RXIM TXIM

RORIM : Receive overrun interrupt mask
bits : 0 - 0 (1 bit)

RTIM : Receive timeout interrupt mask
bits : 1 - 2 (2 bit)

RXIM : Receive FIFO interrupt mask
bits : 2 - 4 (3 bit)

TXIM : Transmit FIFO interrupt mask
bits : 3 - 6 (4 bit)


RIS

Raw interrupt status register
address_offset : 0x18 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RIS RIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RORRIS RTRIS RXRIS TXRIS

RORRIS : receive over run raw interrupt state
bits : 0 - 0 (1 bit)

RTRIS : receive timeout raw interrupt state
bits : 1 - 2 (2 bit)

RXRIS : receive FIFO raw interrupt state
bits : 2 - 4 (3 bit)

TXRIS : transmit FIFOraw interrupt state
bits : 3 - 6 (4 bit)


MIS

Masked interrupt status register
address_offset : 0x1C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MIS MIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RORMIS RTMIS RXMIS TXMIS

RORMIS : receive over run masked interrupt state
bits : 0 - 0 (1 bit)

RTMIS : receive timeout masked interrupt state
bits : 1 - 2 (2 bit)

RXMIS : receive FIFO masked interrupt state
bits : 2 - 4 (3 bit)

TXMIS : transmit FIFO masked interrupt state
bits : 3 - 6 (4 bit)


ICR

Interrupt clear register
address_offset : 0x20 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ICR ICR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RORIC RTIC

RORIC : Clears the SSPRORINTR interrupt
bits : 0 - 0 (1 bit)

RTIC : Clears the SSPRTINTR interrupt
bits : 1 - 2 (2 bit)


DMACR

DMA control register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACR DMACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDMAE TXDMAE

RXDMAE : Receive DMA Enable
bits : 0 - 0 (1 bit)

TXDMAE : Transmit DMA Enable
bits : 1 - 2 (2 bit)


CR1

Control register 1
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR1 CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LBM SSE MS SOD

LBM : Loop back mode
bits : 0 - 0 (1 bit)

SSE : Synchronous serial port enable
bits : 1 - 2 (2 bit)

MS : Master or slave mode select
bits : 2 - 4 (3 bit)

SOD : Slave-mode output disable
bits : 3 - 6 (4 bit)


DR

Data register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DR DR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Data

Data : Transmit/Receive FIFO
bits : 0 - 15 (16 bit)


SR

Status register
address_offset : 0xC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TFE TNF RNE RFF BSY

TFE : Transmit FIFO empty
bits : 0 - 0 (1 bit)

TNF : Transmit FIFO not full
bits : 1 - 2 (2 bit)

RNE : Receive FIFO not empty
bits : 2 - 4 (3 bit)

RFF : Receive FIFO full
bits : 3 - 6 (4 bit)

BSY : PrimeCell SSP busy flag
bits : 4 - 8 (5 bit)



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