Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x40 byte (0x0)
mem_usage : registers
protection : not protected
Control register 0
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSS : Data Size Select
bits : 0 - 3 (4 bit)
Enumeration:
3 : 4-bit
None
4 : 5-bit
None
5 : 6-bit
None
6 : 7-bit
None
7 : 8-bit
None
8 : 9-bit
None
9 : 10-bit
None
10 : 11-bit
None
11 : 12-bit
None
12 : 13-bit
None
13 : 14-bit
None
14 : 15-bit
None
15 : 16-bit
None
End of enumeration elements list.
FRF : Frame format
bits : 4 - 9 (6 bit)
Enumeration:
0 : Motorola
Motorola SPI frame format
1 : TI
TI synchronous serial frame format
2 : NM
National Microwire frame format
End of enumeration elements list.
SPO : SSPCLKOUT polarity
bits : 6 - 12 (7 bit)
SPH : SSPCLKOUT phase
bits : 7 - 14 (8 bit)
SCR : Serial clock rate
bits : 8 - 23 (16 bit)
Clock prescale register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPSDVSR : Clock prescale divisor
bits : 0 - 7 (8 bit)
Interrupt mask set or clear register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RORIM : Receive overrun interrupt mask
bits : 0 - 0 (1 bit)
Enumeration:
0 : Masked
Receive FIFO written to while full condition interrupt is masked
1 : Not Masked
Receive FIFO written to while full condition interrupt is not masked
End of enumeration elements list.
RTIM : Receive timeout interrupt mask
bits : 1 - 2 (2 bit)
Enumeration:
0 : Masked
Receive FIFO not empty or no read prior to timeout period interrupt is masked
1 : Not Masked
Receive FIFO not empty or no read prior to timeout period interrupt is not masked
End of enumeration elements list.
RXIM : Receive FIFO interrupt mask
bits : 2 - 4 (3 bit)
Enumeration:
0 : Masked
Receive FIFO half full or less condition interrupt is masked
1 : Not Masked
Receive FIFO half full or less condition interrupt is not masked
End of enumeration elements list.
TXIM : Transmit FIFO interrupt mask
bits : 3 - 6 (4 bit)
Enumeration:
0 : Masked
Transmit FIFO half empty or less condition interrupt is masked
1 : Not Masked
Transmit FIFO half empty or less condition interrupt is not masked
End of enumeration elements list.
Raw interrupt status register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RORRIS : receive over run raw interrupt state
bits : 0 - 0 (1 bit)
RTRIS : receive timeout raw interrupt state
bits : 1 - 2 (2 bit)
RXRIS : receive FIFO raw interrupt state
bits : 2 - 4 (3 bit)
TXRIS : transmit FIFO raw interrupt state
bits : 3 - 6 (4 bit)
Masked interrupt status register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RORMIS : receive over run masked interrupt state
bits : 0 - 0 (1 bit)
RTMIS : receive timeout masked interrupt state
bits : 1 - 2 (2 bit)
RXMIS : receive FIFO masked interrupt state
bits : 2 - 4 (3 bit)
TXMIS : transmit FIFO masked interrupt state
bits : 3 - 6 (4 bit)
Interrupt clear register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RORIC : Clears the SSPRORINTR interrupt
bits : 0 - 0 (1 bit)
RTIC : Clears the SSPRTINTR interrupt
bits : 1 - 2 (2 bit)
DMA control register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXDMAE : Receive DMA Enable
bits : 0 - 0 (1 bit)
TXDMAE : Transmit DMA Enable
bits : 1 - 2 (2 bit)
Control register 1
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LBM : Loop back mode
bits : 0 - 0 (1 bit)
Enumeration:
0 : Normal
Normal serial port operation enabled
1 : Loopback
Output of transmit serial shifter is connected to input of receive serial shifter internally
End of enumeration elements list.
SSE : Synchronous serial port enable
bits : 1 - 2 (2 bit)
Enumeration:
0 : Disabled
SSP operation disabled
1 : Enabled
SSP operation enabled
End of enumeration elements list.
MS : Master or slave mode select
bits : 2 - 4 (3 bit)
Enumeration:
0 : Master
Device configured as master, default
1 : Slave
Device configured as slave
End of enumeration elements list.
SOD : Slave-mode output disable
bits : 3 - 6 (4 bit)
Enumeration:
0 : Enable
SSP can drive the SSPTXD output in slave mode
1 : Disable
SSP must not drive the SSPTXD output in slave mode
End of enumeration elements list.
Data register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Data : Transmit/Receive FIFO
bits : 0 - 15 (16 bit)
Test control register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ITEN : Integration test enable
bits : 0 - 0 (1 bit)
Enumeration:
0 : Disabled
Normal mode
1 : Enabled
The PrimeCell SSP is placed in integration test mode.
End of enumeration elements list.
TESTFIFO : Test FIFO enable
bits : 1 - 2 (2 bit)
Enumeration:
0 : Disabled
Normal operation
1 : Enabled
When this bit is 1, a write to the TDR writes data into the receive FIFO, and reads from the TDR reads data out of the transmit FIFO.
End of enumeration elements list.
Integration test input register
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXD : Return the value of RXD primary input
bits : 0 - 0 (1 bit)
FSSIN : Return the value of FSSIN primary input
bits : 1 - 2 (2 bit)
CLKIN : Return the value of CLKIN primary input
bits : 2 - 4 (3 bit)
RXDDMACLR : Value to be driven on the intra-chip input
bits : 3 - 6 (4 bit)
TXDMACLR : Value to be driven on the intra-chip input
bits : 4 - 8 (5 bit)
Integration test output register
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXD : Value on the TXD line
bits : 0 - 0 (1 bit)
FSSOUT : Value on the FSSOUT line
bits : 1 - 2 (2 bit)
CLKOUT : Value on the CLKOUT line
bits : 2 - 4 (3 bit)
CTLOE : Value on the OE line
bits : 3 - 6 (4 bit)
OE : Value on the OE line
bits : 4 - 8 (5 bit)
RORINTR : Value on the RORINTR line
bits : 5 - 10 (6 bit)
RTINTR : Value on the RTINTR line
bits : 6 - 12 (7 bit)
RXINTR : Value on the RXINTR line
bits : 7 - 14 (8 bit)
TXINTR : Value on the TXINTR line
bits : 8 - 16 (9 bit)
INTR : Value on the INTR line
bits : 9 - 18 (10 bit)
RXDMABREQ : Value on the TXDMABREQ line
bits : 10 - 20 (11 bit)
RXDMASREQ : Value on the TXDMASREQ line
bits : 11 - 22 (12 bit)
TXDMABREQ : Value on the TXDMABREQ line
bits : 12 - 24 (13 bit)
TXDMASREQ : Value on the TXDMASREQ line
bits : 13 - 26 (14 bit)
Test data register
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : When the TESTFIFO signal is asserted, data is written into the receive FIFO and read out of the transmit FIFO
bits : 0 - 15 (16 bit)
Status register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFE : Transmit FIFO empty
bits : 0 - 0 (1 bit)
Enumeration:
0 : NE
Receive FIFO is not empty
1 : E
Receive FIFO is empty
End of enumeration elements list.
TNF : Transmit FIFO not full
bits : 1 - 2 (2 bit)
Enumeration:
0 : F
Receive FIFO is full
1 : NF
Receive FIFO is not full
End of enumeration elements list.
RNE : Receive FIFO not empty
bits : 2 - 4 (3 bit)
Enumeration:
0 : E
Receive FIFO is empty
1 : NE
Receive FIFO is not empty
End of enumeration elements list.
RFF : Receive FIFO full
bits : 3 - 6 (4 bit)
Enumeration:
0 : NF
Receive FIFO is not full
1 : F
Receive FIFO is full
End of enumeration elements list.
BSY : PrimeCell SSP busy flag
bits : 4 - 8 (5 bit)
Enumeration:
0 : Idle
SSP is idle
1 : Busy
SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty
End of enumeration elements list.
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