SPI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x40 byte (0x0)
mem_usage : registers
protection : not protected

Registers

SPSTAT

SPDAT

SPCLK

SPCON


SPSTAT

SPI Status
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SPDAT

SPI Data
address_offset : 0x2 Bytes (0x0)
access : read-write
reset_value : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SPCLK

SPI Clock Configuration
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SPCON

SPI Configuration
address_offset : 0x6 Bytes (0x0)
access : read-write
reset_value : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPEN SSDIS MSTRS CPOL CPHA SPR1 SPR0

SPEN :
bits : 0 - 0

SSDIS :
bits : 1 - 2

MSTRS :
bits : 2 - 4

CPOL :
bits : 3 - 6

CPHA :
bits : 4 - 8

SPR1 :
bits : 5 - 10

SPR0 :
bits : 6 - 12



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