\n
address_offset : 0x0 Bytes (0x0)
size : 0x40 byte (0x0)
mem_usage : registers
protection : not protected
SPI Status
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPI Data
address_offset : 0x2 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPI Clock Configuration
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPI Configuration
address_offset : 0x6 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPEN :
bits : 0 - 0 (1 bit)
SSDIS :
bits : 1 - 2 (2 bit)
MSTRS :
bits : 2 - 4 (3 bit)
CPOL :
bits : 3 - 6 (4 bit)
CPHA :
bits : 4 - 8 (5 bit)
SPR1 :
bits : 5 - 10 (6 bit)
SPR0 :
bits : 6 - 12 (7 bit)
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.