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SCC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CFG_REG0

CFG_REG4

DLL

CFG_REG5

CFG_REG6

CFG_REG7

CFG_REG1

CFG_REG2

SYS_CFGDATA_RTN

SYS_CFGDATA_OUT

SYS_CFGCTRL

SYS_CFGSTAT

CFG_REG3

AID

ID


CFG_REG0


address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG_REG0 CFG_REG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REMAP

REMAP : 1 = REMAP Block RAM to ZBT
bits : 0 - 0 (1 bit)


CFG_REG4


address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CFG_REG4 CFG_REG4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BRDREV

BRDREV : Board Revision
bits : 0 - 3 (4 bit)


DLL

DLL Lock Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DLL DLL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCKED LOCK_UNLOCK LOCKED_MASKED

LOCKED : Complete Flag
bits : 0 - 0 (1 bit)

LOCK_UNLOCK : Complete Flag
bits : 16 - 39 (24 bit)

LOCKED_MASKED : Error Flag
bits : 24 - 55 (32 bit)


CFG_REG5


address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG_REG5 CFG_REG5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEBUG

DEBUG : Debug: 0 = Serial Wire Debug 1 = JTAG
bits : 5 - 10 (6 bit)


CFG_REG6


address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CFG_REG6 CFG_REG6 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CFG_REG7


address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CFG_REG7 CFG_REG7 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CFG_REG1


address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG_REG1 CFG_REG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCC_LED0 MCC_LED1 MCC_LED2 MCC_LED3 MCC_LED4 MCC_LED5 MCC_LED6 MCC_LED7

MCC_LED0 : MCC LEDs: 0 = OFF 1 = ON
bits : 0 - 0 (1 bit)

Enumeration:

0 : Off

LED is off

1 : On

LED is on

End of enumeration elements list.

MCC_LED1 : MCC LEDs: 0 = OFF 1 = ON
bits : 1 - 2 (2 bit)

Enumeration:

0 : Off

LED is off

1 : On

LED is on

End of enumeration elements list.

MCC_LED2 : MCC LEDs: 0 = OFF 1 = ON
bits : 2 - 4 (3 bit)

Enumeration:

0 : Off

LED is off

1 : On

LED is on

End of enumeration elements list.

MCC_LED3 : MCC LEDs: 0 = OFF 1 = ON
bits : 3 - 6 (4 bit)

Enumeration:

0 : Off

LED is off

1 : On

LED is on

End of enumeration elements list.

MCC_LED4 : MCC LEDs: 0 = OFF 1 = ON
bits : 4 - 8 (5 bit)

Enumeration:

0 : Off

LED is off

1 : On

LED is on

End of enumeration elements list.

MCC_LED5 : MCC LEDs: 0 = OFF 1 = ON
bits : 5 - 10 (6 bit)

Enumeration:

0 : Off

LED is off

1 : On

LED is on

End of enumeration elements list.

MCC_LED6 : MCC LEDs: 0 = OFF 1 = ON
bits : 6 - 12 (7 bit)

Enumeration:

0 : Off

LED is off

1 : On

LED is on

End of enumeration elements list.

MCC_LED7 : MCC LEDs: 0 = OFF 1 = ON
bits : 7 - 14 (8 bit)

Enumeration:

0 : Off

LED is off

1 : On

LED is on

End of enumeration elements list.


CFG_REG2


address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CFG_REG2 CFG_REG2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SYS_CFGDATA_RTN


address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_CFGDATA_RTN SYS_CFGDATA_RTN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SYS_CFGDATA_OUT


address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_CFGDATA_OUT SYS_CFGDATA_OUT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SYS_CFGCTRL


address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_CFGCTRL SYS_CFGCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEVICE RFUNCVAL RW_ACCESS START

DEVICE : Device (value of 0/1/2 for supported clocks
bits : 0 - 11 (12 bit)

RFUNCVAL : Function Value
bits : 20 - 45 (26 bit)

RW_ACCESS : Read/Write Access
bits : 30 - 60 (31 bit)

START : Start: generates interrupt on write to this bit
bits : 31 - 62 (32 bit)


SYS_CFGSTAT


address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_CFGSTAT SYS_CFGSTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMPLETE ERROR

COMPLETE : Complete Flag
bits : 0 - 0 (1 bit)

ERROR : Error Flag
bits : 1 - 2 (2 bit)


CFG_REG3


address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CFG_REG3 CFG_REG3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCC_SWITCHE0 MCC_SWITCHE1 MCC_SWITCHE2 MCC_SWITCHE3 MCC_SWITCHE4 MCC_SWITCHE5 MCC_SWITCHE6 MCC_SWITCHE7

MCC_SWITCHE0 : MCC SWITCHES: 0 = OFF 1 = ON
bits : 0 - 0 (1 bit)

Enumeration:

0 : Off

Switch is off

1 : On

Switch is on

End of enumeration elements list.

MCC_SWITCHE1 : MCC SWITCHES: 0 = OFF 1 = ON
bits : 1 - 2 (2 bit)

Enumeration:

0 : Off

Switch is off

1 : On

Switch is on

End of enumeration elements list.

MCC_SWITCHE2 : MCC SWITCHES: 0 = OFF 1 = ON
bits : 2 - 4 (3 bit)

Enumeration:

0 : Off

Switch is off

1 : On

Switch is on

End of enumeration elements list.

MCC_SWITCHE3 : MCC SWITCHES: 0 = OFF 1 = ON
bits : 3 - 6 (4 bit)

Enumeration:

0 : Off

Switch is off

1 : On

Switch is on

End of enumeration elements list.

MCC_SWITCHE4 : MCC SWITCHES: 0 = OFF 1 = ON
bits : 4 - 8 (5 bit)

Enumeration:

0 : Off

Switch is off

1 : On

Switch is on

End of enumeration elements list.

MCC_SWITCHE5 : MCC SWITCHES: 0 = OFF 1 = ON
bits : 5 - 10 (6 bit)

Enumeration:

0 : Off

Switch is off

1 : On

Switch is on

End of enumeration elements list.

MCC_SWITCHE6 : MCC SWITCHES: 0 = OFF 1 = ON
bits : 6 - 12 (7 bit)

Enumeration:

0 : Off

Switch is off

1 : On

Switch is on

End of enumeration elements list.

MCC_SWITCHE7 : MCC SWITCHES: 0 = OFF 1 = ON
bits : 7 - 14 (8 bit)

Enumeration:

0 : Off

Switch is off

1 : On

Switch is on

End of enumeration elements list.


AID


address_offset : 0xFF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

AID AID read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NUM_CFG_REG MPS2_REV FPGA_BUILD

NUM_CFG_REG : Number of SCC configuration register
bits : 0 - 7 (8 bit)

MPS2_REV : V2M-MPS2 target Board Revision (A=0,B=1,C=2)
bits : 20 - 43 (24 bit)

FPGA_BUILD : FPGA Build Number
bits : 24 - 55 (32 bit)


ID


address_offset : 0xFFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ID ID read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 APP_REV PRI_NUM IP_ARCH APP_NOTE_VAR IMPLEMENTER_ID

APP_REV : Application note IP revision number
bits : 0 - 3 (4 bit)

PRI_NUM : Primary Part Number: 383 = AN383
bits : 4 - 15 (12 bit)

IP_ARCH : IP Architecture: 0x4 = AHB
bits : 16 - 35 (20 bit)

APP_NOTE_VAR : Application note IP variant number
bits : 20 - 43 (24 bit)

IMPLEMENTER_ID : Implementer ID: 0x41 = ARM
bits : 24 - 55 (32 bit)



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