\n
address_offset : 0x0 Bytes (0x0)
size : 0xC04 byte (0x0)
mem_usage : registers
protection : not protected
Watchdog Load Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Watchdog Raw Interrupt Status Register
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RIS : Raw watchdog Interrupt
bits : 0 - 0 (1 bit)
Watchdog Mask Interrupt Status Register
address_offset : 0x14 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MIS : Masked Watchdog Interrupt
bits : 0 - 0 (1 bit)
Watchdog Value Register
address_offset : 0x4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Watchdog Control Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTEN : Enable the interrupt event
bits : 0 - 0 (1 bit)
Enumeration:
0 : Disable
Disable Watchdog interrupt
1 : Enable
ENable Watchdog interrupt.
End of enumeration elements list.
RESEN : Enable watchdog reset output
bits : 1 - 1 (1 bit)
Enumeration:
0 : Disable
Disable Watchdog reset
1 : Enable
ENable Watchdog reset
End of enumeration elements list.
Watchdog Interrupt Clear Register
address_offset : 0xC Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INT : Interrupt
bits : 0 - 0 (1 bit)
Watchdog Lock Register
address_offset : 0xC00 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.