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SYSINFO

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

SYS_VERSION

SYS_CONFIG

PIDR4

PIDR0

PIDR1

PIDR2

PIDR3

CIDR0

CIDR1

CIDR2

CIDR3


SYS_VERSION

System Version Register
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SYS_VERSION SYS_VERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PART_NUMBER DESIGNER_ID MINOR_REVISION MAJOR_REVISION CONFIGURATION

PART_NUMBER : Part Number for the SSE-200
bits : 0 - 11 (12 bit)

DESIGNER_ID : Arm Product with designer code 0x41
bits : 12 - 31 (20 bit)

MINOR_REVISION : Minor Revision
bits : 20 - 43 (24 bit)

MAJOR_REVISION : Major Revision
bits : 24 - 51 (28 bit)

CONFIGURATION : CONFIGURATION for SSE-200 r2: 0x2
bits : 28 - 59 (32 bit)


SYS_CONFIG

System Hardware Configuration register
address_offset : 0x4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SYS_CONFIG SYS_CONFIG read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRAM_NUM_BANK SRAM_ADDR_WIDTH CPU0_HAS_TCM CPU1_HAS_TCM HAS_CRYPTO CPU0_TCM_BANK_NUM CPU1_TCM_BANK_NUM CPU0_TYPE CPU1_TYPE

SRAM_NUM_BANK : SRAM Number of Banks
bits : 0 - 3 (4 bit)

SRAM_ADDR_WIDTH : SRAM Bank Address Width
bits : 4 - 12 (9 bit)

CPU0_HAS_TCM : CPU 0 has Data TCM:
bits : 9 - 18 (10 bit)

Enumeration:

0 : No

CPU 0 does not have Data TCM

1 : Yes

CPU 0 has Data TCM

End of enumeration elements list.

CPU1_HAS_TCM : CPU 1 has Data TCM:
bits : 10 - 20 (11 bit)

Enumeration:

0 : No

CPU 1 does not have Data TCM

1 : Yes

CPU 1 has Data TCM

End of enumeration elements list.

HAS_CRYPTO : Whether CryptoCell Included:
bits : 12 - 24 (13 bit)

Enumeration:

0 : No

CryptoCell Not Included

1 : Yes

CryptoCell Included

End of enumeration elements list.

CPU0_TCM_BANK_NUM : The SRAM Bank that maps CPU0 Data TCM
bits : 16 - 35 (20 bit)

CPU1_TCM_BANK_NUM : Number of SRAM banks
bits : 20 - 43 (24 bit)

Enumeration:

0x3 : Four

4 SRAM Banks

0x2 : Three

3 SRAM Banks

0x1 : Two

2 SRAM Banks

0x0 : Otherwise

Otherwise

End of enumeration elements list.

CPU0_TYPE : CPU 0 Core Type
bits : 24 - 51 (28 bit)

Enumeration:

0x0 : Not Exist

Does Not Exist

0x2 : CM33

Cortex-M33 Core

End of enumeration elements list.

CPU1_TYPE : CPU 1 Core Type
bits : 28 - 59 (32 bit)

Enumeration:

0x0 : Not Exist

Does Not Exist

0x2 : CM33

Cortex-M33 Core

End of enumeration elements list.


PIDR4

Peripheral ID 4
address_offset : 0xFD0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIDR4 PIDR4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PIDR0

Peripheral ID 0
address_offset : 0xFE0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIDR0 PIDR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PIDR1

Peripheral ID 1
address_offset : 0xFE4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIDR1 PIDR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PIDR2

Peripheral ID 2
address_offset : 0xFE8 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIDR2 PIDR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PIDR3

Peripheral ID 3
address_offset : 0xFEC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIDR3 PIDR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CIDR0

Component ID 0
address_offset : 0xFF0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIDR0 CIDR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CIDR1

Component ID 1
address_offset : 0xFF4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIDR1 CIDR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CIDR2

Component ID 2
address_offset : 0xFF8 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIDR2 CIDR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CIDR3

Component ID 3
address_offset : 0xFFC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIDR3 CIDR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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