\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
System Version Register
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PART_NUMBER : Part Number for the SSE-200
bits : 0 - 11 (12 bit)
DESIGNER_ID : Arm Product with designer code 0x41
bits : 12 - 31 (20 bit)
MINOR_REVISION : Minor Revision
bits : 20 - 43 (24 bit)
MAJOR_REVISION : Major Revision
bits : 24 - 51 (28 bit)
CONFIGURATION : CONFIGURATION for SSE-200 r2: 0x2
bits : 28 - 59 (32 bit)
System Hardware Configuration register
address_offset : 0x4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SRAM_NUM_BANK : SRAM Number of Banks
bits : 0 - 3 (4 bit)
SRAM_ADDR_WIDTH : SRAM Bank Address Width
bits : 4 - 12 (9 bit)
CPU0_HAS_TCM : CPU 0 has Data TCM:
bits : 9 - 18 (10 bit)
Enumeration:
0 : No
CPU 0 does not have Data TCM
1 : Yes
CPU 0 has Data TCM
End of enumeration elements list.
CPU1_HAS_TCM : CPU 1 has Data TCM:
bits : 10 - 20 (11 bit)
Enumeration:
0 : No
CPU 1 does not have Data TCM
1 : Yes
CPU 1 has Data TCM
End of enumeration elements list.
HAS_CRYPTO : Whether CryptoCell Included:
bits : 12 - 24 (13 bit)
Enumeration:
0 : No
CryptoCell Not Included
1 : Yes
CryptoCell Included
End of enumeration elements list.
CPU0_TCM_BANK_NUM : The SRAM Bank that maps CPU0 Data TCM
bits : 16 - 35 (20 bit)
CPU1_TCM_BANK_NUM : Number of SRAM banks
bits : 20 - 43 (24 bit)
Enumeration:
0x3 : Four
4 SRAM Banks
0x2 : Three
3 SRAM Banks
0x1 : Two
2 SRAM Banks
0x0 : Otherwise
Otherwise
End of enumeration elements list.
CPU0_TYPE : CPU 0 Core Type
bits : 24 - 51 (28 bit)
Enumeration:
0x0 : Not Exist
Does Not Exist
0x2 : CM33
Cortex-M33 Core
End of enumeration elements list.
CPU1_TYPE : CPU 1 Core Type
bits : 28 - 59 (32 bit)
Enumeration:
0x0 : Not Exist
Does Not Exist
0x2 : CM33
Cortex-M33 Core
End of enumeration elements list.
Peripheral ID 4
address_offset : 0xFD0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Peripheral ID 0
address_offset : 0xFE0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Peripheral ID 1
address_offset : 0xFE4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Peripheral ID 2
address_offset : 0xFE8 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Peripheral ID 3
address_offset : 0xFEC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Component ID 0
address_offset : 0xFF0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Component ID 1
address_offset : 0xFF4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Component ID 2
address_offset : 0xFF8 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Component ID 3
address_offset : 0xFFC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
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