\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
Secure Debug Configuration Status
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DBGEN_I_STATUS : Debug enable value
bits : 0 - 0 (1 bit)
Enumeration:
1 : enable
debug enable
0 : disable
debug disable
End of enumeration elements list.
DBGEN_SEL_STATUS : Debug enable selector value
bits : 1 - 2 (2 bit)
Enumeration:
1 : enable
debug enable selector
0 : disable
debug disable selector
End of enumeration elements list.
NIDEN_I_STATUS : Non-invasive debug enable value
bits : 2 - 4 (3 bit)
Enumeration:
1 : enable
non-invasive debug enable
0 : disable
non-invasive debug disable
End of enumeration elements list.
NIDEN_SEL_STATUS : Non-invasive debug enable selector value
bits : 3 - 6 (4 bit)
Enumeration:
1 : enable
non-invasive debug enable selector
0 : disable
non-invasive debug disable selector
End of enumeration elements list.
SPIDEN_I_STATUS : Secure privilege invasive debug enable value
bits : 4 - 8 (5 bit)
Enumeration:
1 : enable
Secure privilege invasive debug enable
0 : disable
Secure privilege invasive debug disable
End of enumeration elements list.
SPIDEN_SEL_STATUS : Secure privilege invasive debug enable selector value
bits : 5 - 10 (6 bit)
Enumeration:
1 : enable
Secure privilege invasive debug enable selector
0 : disable
Secure privilege invasive debug disable selector
End of enumeration elements list.
SPNIDEN_STATUS : Secure privilege non-invasive debug enable value
bits : 6 - 12 (7 bit)
Enumeration:
1 : enable
Secure privilege non-invasive debug enable
0 : disable
Secure privilege non-invasive debug disable
End of enumeration elements list.
SPNIDEN_SEL_STATUS : Secure privilege non-invasive debug enable selector value
bits : 7 - 14 (8 bit)
Enumeration:
1 : enable
Secure privilege non-invasive debug enable selector
0 : disable
Secure privilege non-invasive debug disable selector
End of enumeration elements list.
Fast Clock Divider Configuration
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FCLKDIV : FCLK from MAINCLK Clock Divider Ratio Request
bits : 0 - 4 (5 bit)
FCLKDIV_CUR : Clock Divider Current Value.
bits : 16 - 36 (21 bit)
access : read-only
Reset Syndrome
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PoR : Power-on
bits : 0 - 0 (1 bit)
access : write-only
NSWD : Non-secure watchdog
bits : 1 - 2 (2 bit)
access : write-only
SWD : Secure watchdog
bits : 2 - 4 (3 bit)
access : write-only
S32KWD : Watchdog on the S32KCLK clock
bits : 3 - 6 (4 bit)
access : write-only
SYSRSTREQ0 : CPU 0 System Reset Request
bits : 4 - 8 (5 bit)
access : write-only
SYSRSTREQ1 : CPU 1 System Reset Request
bits : 5 - 10 (6 bit)
access : write-only
LOCKUP0 : CPU 0 Lock-up Status
bits : 6 - 12 (7 bit)
access : write-only
LOCKUP1 : CPU 1 Lock-up Status
bits : 7 - 14 (8 bit)
access : write-only
RESETREQ : External Reset Request
bits : 8 - 16 (9 bit)
access : write-only
SWRESETREQ : Software Reset Request
bits : 9 - 18 (10 bit)
access : write-only
Reset Mask
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NSWD_EN : Enable NON-SECURE WATCHDOG Reset
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
1 : enabled
Enable NON-SECURE WATCHDOG Reset
0 : disabled
Disabled NON-SECURE WATCHDOG Reset
End of enumeration elements list.
SYSRSTREQ0_EN : Enable Merging CPU 0 System Reset Request
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
1 : enabled
Enable Merging CPU 0 System Reset Request
0 : disabled
Disabled Merging CPU 0 System Reset Request
End of enumeration elements list.
SYSRSTREQ1_EN : Enable Merging CPU 0 System Reset Request
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
1 : enabled
Enable Merging CPU 1 System Reset Request
0 : disabled
Disabled Merging CPU 1 System Reset Request
End of enumeration elements list.
Software Reset
address_offset : 0x108 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SWRESETREQ : High Active Software Reset Request
bits : 9 - 18 (10 bit)
access : write-only
General Purpose Retention
address_offset : 0x10C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GRETREG : General Purpose Retention Register
bits : 0 - 15 (16 bit)
access : read-write
Initial Secure Reset Vector Register For CPU 0
address_offset : 0x110 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INITSVTOR0 : Default Secure Vector table offset at reset for CPU 0
bits : 7 - 38 (32 bit)
access : read-write
Initial Secure Reset Vector Register For CPU 1
address_offset : 0x114 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INITSVTOR1 : Default Secure Vector table offset at reset for CPU 1
bits : 7 - 38 (32 bit)
access : read-write
CPU Boot wait control after reset
address_offset : 0x118 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU0WAIT : CPU 0 waits at boot and whether CPU1 powers up
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : normally or power-up
CPU0 boot normally. From Power ON reset, nSRST reset or Watchdog Reset, CPU 1 powers up
1 : wait or no power-up
CPU0 wait. From Power ON reset, nSRST reset or Watchdog Reset, CPU 1 do not power up
End of enumeration elements list.
CPU1WAIT : CPU 1 waits at boot and whether CPU0 powers up
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : normally or power-up
CPU1 boot normally. From Power ON reset, nSRST reset or Watchdog Reset, CPU 0 powers up
1 : wait or no power-up
CPU1 wait. From Power ON reset, nSRST reset or Watchdog Reset, CPU 0 do not power up
End of enumeration elements list.
NMI Enable Register
address_offset : 0x11C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU0_INTNMI_ENABLE : CPU0 Internally Sourced NMI Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
1 : enable
CPU0 Internally Sourced NMI Enabled
0 : disabled
CPU0 Internally Sourced NMI Disabled
End of enumeration elements list.
CPU1_INTNMI_ENABLE : CPU1 Internally Sourced NMI Enable
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
1 : enable
CPU1 Internally Sourced NMI Enabled
0 : disabled
CPU1 Internally Sourced NMI Disabled
End of enumeration elements list.
CPU0_EXPNMI_ENABLE : CPU0 Externally Sourced NMI Enable
bits : 16 - 32 (17 bit)
access : read-write
Enumeration:
1 : enable
CPU0 Externally Sourced NMI Enabled
0 : disabled
CPU0 Externally Sourced NMI Disabled
End of enumeration elements list.
CPU1_EXPNMI_ENABLE : CPU1 Externally Sourced NMI Enable
bits : 17 - 34 (18 bit)
access : read-write
Enumeration:
1 : enable
CPU1 Externally Sourced NMI Enabled
0 : disabled
CPU1 Externally Sourced NMI Disabled
End of enumeration elements list.
WIC request and acknowledge handshake
address_offset : 0x120 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU0WICEN_STATUS : CPU 0 WIC Enable Request Status
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
1 : enable
CPU 0 WIC request enabled
0 : disabled
CPU 0 WIC request disabled
End of enumeration elements list.
CPU1WICEN_STATUS : CPU 1 WIC Enable Request Status
bits : 1 - 2 (2 bit)
access : read-only
Enumeration:
1 : enable
CPU 1 WIC request enabled
0 : disabled
CPU 1 WIC request disabled
End of enumeration elements list.
CPU0WICEN_SET : High Active CPU 0 WIC Enable Request Set
bits : 4 - 8 (5 bit)
access : write-only
CPU1WICEN_SET : High Active CPU 1 WIC Enable Request Set
bits : 5 - 10 (6 bit)
access : write-only
CPU0WICEN_CLR : High Active CPU 0 WIC Enable Request Clear
bits : 8 - 16 (9 bit)
access : write-only
CPU1WICEN_CLR : High Active CPU 1 WIC Enable Request Clear
bits : 9 - 18 (10 bit)
access : write-only
CPU0WICRDY : CPU 0 WIC Enable Acknowledge
bits : 16 - 32 (17 bit)
access : read-only
Enumeration:
1 : enabled
CPU 0 WIC Enabled
0 : disabled
CPU 0 WIC Disabled
End of enumeration elements list.
CPU1WICRDY : CPU 1 WIC Enable Acknowledge
bits : 17 - 34 (18 bit)
access : read-only
Enumeration:
1 : enabled
CPU 1 WIC Enabled
0 : disabled
CPU 1 WIC Disabled
End of enumeration elements list.
External Wakeup Control
address_offset : 0x124 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EWC0EN_STATUS : External Wakeup Controller 0 Enable
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
1 : enable
External Wakeup Controller 0 Enabled
0 : disabled
External Wakeup Controller 0 Disabled
End of enumeration elements list.
EWC1EN_STATUS : External Wakeup Controller 1 Enable
bits : 1 - 2 (2 bit)
access : read-only
Enumeration:
1 : enable
External Wakeup Controller 1 Enabled
0 : disabled
External Wakeup Controller 1 Disabled
End of enumeration elements list.
EWC0EN_SET : EHigh Active External Wakeup Controller 0 Set
bits : 4 - 8 (5 bit)
access : write-only
EWC1EN_SET : High Active External Wakeup Controller 1 Set
bits : 5 - 10 (6 bit)
access : write-only
EWC0EN_CLR : High Active External Wakeup Controller 0 Clear
bits : 8 - 16 (9 bit)
access : write-only
EWC1EN_CLR : High Active External Wakeup Controller 1 Clear
bits : 9 - 18 (10 bit)
access : write-only
System Clock Divider Configuration
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCLKDIV : SYSCLK from FCLK Clock Divider Ratio Request
bits : 0 - 4 (5 bit)
SYSCLKDIV_CUR : Clock Divider Current Value
bits : 16 - 36 (21 bit)
access : read-only
Clock Force
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAINCLK_FORCE : Force MAINCLK to run when set to HIGH
bits : 0 - 0 (1 bit)
SYSSYSCLK_FORCE : Force Base element Local SYSCLK to run when set to HIGH
bits : 1 - 2 (2 bit)
SYSFCLK_FORCE : Force Base element Local FCLK to run when set to HIGH
bits : 2 - 4 (3 bit)
SRAMSYSCLK_FORCE : Force SRAM Local SYSCLK to run when set to HIGH
bits : 3 - 6 (4 bit)
SRAMFCLK_FORCE : Force SRAM Local FCLK to run when set to HIGH
bits : 4 - 8 (5 bit)
CPUSYSCLK_FORCE : Force all CPU SYSCLK to run when set to HIGH
bits : 5 - 10 (6 bit)
CPUFCLK_FORCE : Force all CPU FCLK to run when set to HIGH
bits : 6 - 12 (7 bit)
CRYPTOSYSCLK_FORCE : Force all CryptoCell clocks to run when set to HIGH
bits : 7 - 14 (8 bit)
FCLKHINTGATE_ENABLE : Enable FCLK gating by HINTSYSCLKEN when CPU 1 is OFF
bits : 8 - 16 (9 bit)
Enumeration:
1 : enable
Enable FCLK gating by HINTSYSCLKEN when CPU 1 is OFF
0 : latency
improve SRAM3 access latency at the cost of increased power consumption
End of enumeration elements list.
External Wakeup Control
address_offset : 0x200 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
S_PD_SYS_ON : Enable PD_SYS ON Sensitivity
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
1 : enable
Keep PD_SYS awake after powered ON
End of enumeration elements list.
S_PD_CPU0CORE_ON : Tied to HIGH
bits : 1 - 2 (2 bit)
access : read-only
Enumeration:
1 : high
PD_SYS always tries to stay ON if PD_CPU0CORE is ON
End of enumeration elements list.
S_PD_CPU1CORE_ON : Tied to HIGH
bits : 2 - 4 (3 bit)
access : read-only
Enumeration:
1 : high
PD_SYS always tries to stay ON if PD_CPU1CORE is ON
End of enumeration elements list.
S_PD_SRAM0_ON : Tied to HIGH
bits : 3 - 6 (4 bit)
access : read-only
Enumeration:
1 : high
PD_SYS always tries to keep ON if SRAM0 power domain is ON
End of enumeration elements list.
S_PD_SRAM1_ON : Tied to HIGH
bits : 4 - 8 (5 bit)
access : read-only
Enumeration:
1 : high
PD_SYS always tries to keep ON if SRAM1 power domain is ON
End of enumeration elements list.
S_PD_SRAM2_ON : Tied to HIGH
bits : 5 - 10 (6 bit)
access : read-only
Enumeration:
1 : high
PD_SYS always tries to keep ON if SRAM2 power domain is ON
End of enumeration elements list.
S_PD_SRAM3_ON : Tied to HIGH
bits : 6 - 12 (7 bit)
access : read-only
Enumeration:
1 : high
PD_SYS always tries to keep ON if SRAM3 power domain is ON
End of enumeration elements list.
S_PD_CRYPTO_ON : Tied to HIGH
bits : 12 - 24 (13 bit)
access : read-only
Enumeration:
1 : high
PD_SYS always tries to keep ON if S_PD_CRYPTO_ON is ON
End of enumeration elements list.
S_PD_EXP0_IN : Enable PDEXPIN[0] signal Sensitivity
bits : 16 - 32 (17 bit)
access : read-write
Enumeration:
1 : enable
Enable PDEXPIN[0] signal Sensitivity.
0 : disabled
Disable PDEXPIN[0] signal Sensitivity.
End of enumeration elements list.
S_PD_EXP1_IN : Enable PDEXPIN[1] signal Sensitivity
bits : 17 - 34 (18 bit)
access : read-write
Enumeration:
1 : enable
Enable PDEXPIN[1] signal Sensitivity.
0 : disabled
Disable PDEXPIN[1] signal Sensitivity.
End of enumeration elements list.
S_PD_EXP2_IN : Enable PDEXPIN[2] signal Sensitivity
bits : 18 - 36 (19 bit)
access : read-write
Enumeration:
1 : enable
Enable PDEXPIN[2] signal Sensitivity.
0 : disabled
Disable PDEXPIN[2] signal Sensitivity.
End of enumeration elements list.
S_PD_EXP3_IN : Enable PDEXPIN[3] signal Sensitivity
bits : 19 - 38 (20 bit)
access : read-write
Enumeration:
1 : enable
Enable PDEXPIN[3] signal Sensitivity.
0 : disabled
Disable PDEXPIN[3] signal Sensitivity.
End of enumeration elements list.
Power Control Depedendency Matrix PD_SRAM0 Power Domain Sensitivity
address_offset : 0x20C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
S_PD_SYS_ON : Enable sensitivity to PD_SYS
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
1 : enable
Enable sensitivity to PD_SYS
0 : disable
Disable sensitivity to PD_SYS
End of enumeration elements list.
S_PD_CPU0CORE_ON : Enable sensitivity to PD_CPU0CORE
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
1 : enable
Enable sensitivity to PD_CPU0CORE
0 : disable
Disable sensitivity to PD_CPU0CORE
End of enumeration elements list.
S_PD_CPU1CORE_ON : Enable sensitivity to PD_CPU1CORE
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
1 : enable
Enable sensitivity to PD_CPU1CORE
0 : disable
Disable sensitivity to PD_CPU1CORE
End of enumeration elements list.
S_PD_SRAM0_ON : Enable sensitivity to PD_SRAM0
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
1 : enable
Enable sensitivity to PD_SRAM0
0 : disable
Disable sensitivity to PD_SRAM0
End of enumeration elements list.
S_PD_SRAM1_ON : Tied LOW
bits : 4 - 8 (5 bit)
access : read-only
Enumeration:
0 : Low
Ignores PD_SRAM1 state
End of enumeration elements list.
S_PD_SRAM2_ON : Tied LOW
bits : 5 - 10 (6 bit)
access : read-only
Enumeration:
0 : Low
Ignores PD_SRAM2 state
End of enumeration elements list.
S_PD_SRAM3_ON : Tied LOW
bits : 6 - 12 (7 bit)
access : read-only
Enumeration:
0 : Low
Ignores PD_SRAM3 state
End of enumeration elements list.
S_PD_CRYPTO_ON : Tied LOW
bits : 12 - 24 (13 bit)
access : read-only
Enumeration:
0 : Low
Ignores PD_CRYPTO
End of enumeration elements list.
S_PD_EXP0_IN : Enable PDEXPIN[0] signal Sensitivity
bits : 16 - 32 (17 bit)
access : read-write
Enumeration:
1 : enable
Enable PDEXPIN[0] signal Sensitivity
0 : disable
Disable PDEXPIN[0] signal Sensitivity
End of enumeration elements list.
S_PD_EXP1_IN : Enable PDEXPIN[1] signal Sensitivity
bits : 17 - 34 (18 bit)
access : read-write
Enumeration:
1 : enable
Enable PDEXPIN[1] signal Sensitivity
0 : disable
Disable PDEXPIN[1] signal Sensitivity
End of enumeration elements list.
S_PD_EXP2_IN : Enable PDEXPIN[2] signal Sensitivity
bits : 18 - 36 (19 bit)
access : read-write
Enumeration:
1 : enable
Enable PDEXPIN[2] signal Sensitivity
0 : disable
Disable PDEXPIN[2] signal Sensitivity
End of enumeration elements list.
S_PD_EXP3_IN : Enable PDEXPIN[3] signal Sensitivity
bits : 19 - 38 (20 bit)
access : read-write
Enumeration:
1 : enable
Enable PDEXPIN[3] signal Sensitivity
0 : disable
Disable PDEXPIN[3] signal Sensitivity
End of enumeration elements list.
Power Control Depedendency Matrix PD_SRAM1 Power Domain Sensitivity
address_offset : 0x210 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
S_PD_SYS_ON : Enable sensitivity to PD_SYS
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
1 : enable
Enable sensitivity to PD_SYS
0 : disable
Disable sensitivity to PD_SYS
End of enumeration elements list.
S_PD_CPU0CORE_ON : Enable sensitivity to PD_CPU0CORE
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
1 : enable
Enable sensitivity to PD_CPU0CORE
0 : disable
Disable sensitivity to PD_CPU0CORE
End of enumeration elements list.
S_PD_CPU1CORE_ON : Enable sensitivity to PD_CPU1CORE
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
1 : enable
Enable sensitivity to PD_CPU1CORE
0 : disable
Disable sensitivity to PD_CPU1CORE
End of enumeration elements list.
S_PD_SRAM0_ON : Tied LOW
bits : 3 - 6 (4 bit)
access : read-only
Enumeration:
0 : Low
Ignores PD_SRAM0 state
End of enumeration elements list.
S_PD_SRAM1_ON : Enable sensitivity to PD_SRAM1
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
1 : enable
Enable sensitivity to PD_SRAM1
0 : disable
Disable sensitivity to PD_SRAM1
End of enumeration elements list.
S_PD_SRAM2_ON : Tied LOW
bits : 5 - 10 (6 bit)
access : read-only
Enumeration:
0 : Low
Ignores PD_SRAM2 state
End of enumeration elements list.
S_PD_SRAM3_ON : Tied LOW
bits : 6 - 12 (7 bit)
access : read-only
Enumeration:
0 : Low
Ignores PD_SRAM3 state
End of enumeration elements list.
S_PD_CRYPTO_ON : Tied LOW
bits : 12 - 24 (13 bit)
access : read-only
Enumeration:
0 : Low
Ignores PD_CRYPTO
End of enumeration elements list.
S_PD_EXP0_IN : Enable PDEXPIN[0] signal Sensitivity
bits : 16 - 32 (17 bit)
access : read-write
Enumeration:
1 : enable
Enable PDEXPIN[0] signal Sensitivity
0 : disable
Disable PDEXPIN[0] signal Sensitivity
End of enumeration elements list.
S_PD_EXP1_IN : Enable PDEXPIN[1] signal Sensitivity
bits : 17 - 34 (18 bit)
access : read-write
Enumeration:
1 : enable
Enable PDEXPIN[1] signal Sensitivity
0 : disable
Disable PDEXPIN[1] signal Sensitivity
End of enumeration elements list.
S_PD_EXP2_IN : Enable PDEXPIN[2] signal Sensitivity
bits : 18 - 36 (19 bit)
access : read-write
Enumeration:
1 : enable
Enable PDEXPIN[2] signal Sensitivity
0 : disable
Disable PDEXPIN[2] signal Sensitivity
End of enumeration elements list.
S_PD_EXP3_IN : Enable PDEXPIN[3] signal Sensitivity
bits : 19 - 38 (20 bit)
access : read-write
Enumeration:
1 : enable
Enable PDEXPIN[3] signal Sensitivity
0 : disable
Disable PDEXPIN[3] signal Sensitivity
End of enumeration elements list.
Power Control Depedendency Matrix PD_SRAM2 Power Domain Sensitivity
address_offset : 0x214 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
S_PD_SYS_ON : Enable sensitivity to PD_SYS
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
1 : enable
Enable sensitivity to PD_SYS
0 : disable
Disable sensitivity to PD_SYS
End of enumeration elements list.
S_PD_CPU0CORE_ON : Enable sensitivity to PD_CPU0CORE
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
1 : enable
Enable sensitivity to PD_CPU0CORE
0 : disable
Disable sensitivity to PD_CPU0CORE
End of enumeration elements list.
S_PD_CPU1CORE_ON : Enable sensitivity to PD_CPU1CORE
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
1 : enable
Enable sensitivity to PD_CPU1CORE
0 : disable
Disable sensitivity to PD_CPU1CORE
End of enumeration elements list.
S_PD_SRAM0_ON : Tied LOW
bits : 3 - 6 (4 bit)
access : read-only
Enumeration:
0 : Low
Ignores PD_SRAM0 state
End of enumeration elements list.
S_PD_SRAM1_ON : Tied LOW
bits : 4 - 8 (5 bit)
access : read-only
Enumeration:
0 : Low
Ignores PD_SRAM1 state
End of enumeration elements list.
S_PD_SRAM2_ON : Enable sensitivity to PD_SRAM2
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
1 : enable
Enable sensitivity to PD_SRAM2
0 : disable
Disable sensitivity to PD_SRAM2
End of enumeration elements list.
S_PD_SRAM3_ON : Tied LOW
bits : 6 - 12 (7 bit)
access : read-only
Enumeration:
0 : Low
Ignores PD_SRAM3 state
End of enumeration elements list.
S_PD_CRYPTO_ON : Tied LOW
bits : 12 - 24 (13 bit)
access : read-only
Enumeration:
0 : Low
Ignores PD_CRYPTO
End of enumeration elements list.
S_PD_EXP0_IN : Enable PDEXPIN[0] signal Sensitivity
bits : 16 - 32 (17 bit)
access : read-write
Enumeration:
1 : enable
Enable PDEXPIN[0] signal Sensitivity
0 : disable
Disable PDEXPIN[0] signal Sensitivity
End of enumeration elements list.
S_PD_EXP1_IN : Enable PDEXPIN[1] signal Sensitivity
bits : 17 - 34 (18 bit)
access : read-write
Enumeration:
1 : enable
Enable PDEXPIN[1] signal Sensitivity
0 : disable
Disable PDEXPIN[1] signal Sensitivity
End of enumeration elements list.
S_PD_EXP2_IN : Enable PDEXPIN[2] signal Sensitivity
bits : 18 - 36 (19 bit)
access : read-write
Enumeration:
1 : enable
Enable PDEXPIN[2] signal Sensitivity
0 : disable
Disable PDEXPIN[2] signal Sensitivity
End of enumeration elements list.
S_PD_EXP3_IN : Enable PDEXPIN[3] signal Sensitivity
bits : 19 - 38 (20 bit)
access : read-write
Enumeration:
1 : enable
Enable PDEXPIN[3] signal Sensitivity
0 : disable
Disable PDEXPIN[3] signal Sensitivity
End of enumeration elements list.
Power Control Depedendency Matrix PD_SRAM3 Power Domain Sensitivity
address_offset : 0x218 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
S_PD_SYS_ON : Enable sensitivity to PD_SYS
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
1 : enable
Enable sensitivity to PD_SYS
0 : disable
Disable sensitivity to PD_SYS
End of enumeration elements list.
S_PD_CPU0CORE_ON : Enable sensitivity to PD_CPU0CORE
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
1 : enable
Enable sensitivity to PD_CPU0CORE
0 : disable
Disable sensitivity to PD_CPU0CORE
End of enumeration elements list.
S_PD_CPU1CORE_ON : Enable sensitivity to PD_CPU1CORE
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
1 : enable
Enable sensitivity to PD_CPU1CORE
0 : disable
Disable sensitivity to PD_CPU1CORE
End of enumeration elements list.
S_PD_SRAM0_ON : Tied LOW
bits : 3 - 6 (4 bit)
access : read-only
Enumeration:
0 : Low
Ignores PD_SRAM0 state
End of enumeration elements list.
S_PD_SRAM1_ON : Tied LOW
bits : 4 - 8 (5 bit)
access : read-only
Enumeration:
0 : Low
Ignores PD_SRAM1 state
End of enumeration elements list.
S_PD_SRAM2_ON : Tied LOW
bits : 5 - 10 (6 bit)
access : read-only
Enumeration:
0 : Low
Ignores PD_SRAM2 state
End of enumeration elements list.
S_PD_SRAM3_ON : Enable sensitivity to PD_SRAM3
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
1 : enable
Enable sensitivity to PD_SRAM3
0 : disable
Disable sensitivity to PD_SRAM3
End of enumeration elements list.
S_PD_CRYPTO_ON : Tied LOW
bits : 12 - 24 (13 bit)
access : read-only
Enumeration:
0 : Low
Ignores PD_CRYPTO
End of enumeration elements list.
S_PD_EXP0_IN : Enable PDEXPIN[0] signal Sensitivity
bits : 16 - 32 (17 bit)
access : read-write
Enumeration:
1 : enable
Enable PDEXPIN[0] signal Sensitivity
0 : disable
Disable PDEXPIN[0] signal Sensitivity
End of enumeration elements list.
S_PD_EXP1_IN : Enable PDEXPIN[1] signal Sensitivity
bits : 17 - 34 (18 bit)
access : read-write
Enumeration:
1 : enable
Enable PDEXPIN[1] signal Sensitivity
0 : disable
Disable PDEXPIN[1] signal Sensitivity
End of enumeration elements list.
S_PD_EXP2_IN : Enable PDEXPIN[2] signal Sensitivity
bits : 18 - 36 (19 bit)
access : read-write
Enumeration:
1 : enable
Enable PDEXPIN[2] signal Sensitivity
0 : disable
Disable PDEXPIN[2] signal Sensitivity
End of enumeration elements list.
S_PD_EXP3_IN : Enable PDEXPIN[3] signal Sensitivity
bits : 19 - 38 (20 bit)
access : read-write
Enumeration:
1 : enable
Enable PDEXPIN[3] signal Sensitivity
0 : disable
Disable PDEXPIN[3] signal Sensitivity
End of enumeration elements list.
Secure Debug Configuration Set
address_offset : 0x4 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DBGEN_I_SET : High active debug enable set control
bits : 0 - 0 (1 bit)
DBGEN_SEL_SET : Debug enable selector set control
bits : 1 - 2 (2 bit)
Enumeration:
1 : enable
debug enable selector set control
0 : disable
debug disable selector set control
End of enumeration elements list.
NIDEN_I_SET : Non-invasive debug enable set control
bits : 2 - 4 (3 bit)
Enumeration:
1 : enable
non-invasive debug enable set control
0 : disable
non-invasive debug disable set control
End of enumeration elements list.
NIDEN_SEL_SET : Non-invasive debug enable selector set control
bits : 3 - 6 (4 bit)
Enumeration:
1 : enable
non-invasive debug enable selector set control
0 : disable
non-invasive debug disable selector set control
End of enumeration elements list.
SPIDEN_I_SET : Secure privilege invasive debug enable set control
bits : 4 - 8 (5 bit)
Enumeration:
1 : enable
Secure privilege invasive debug enable set control
0 : disable
Secure privilege invasive debug disable set control
End of enumeration elements list.
SPIDEN_SEL_SET : Secure privilege invasive debug enable selector set control
bits : 5 - 10 (6 bit)
Enumeration:
1 : enable
Secure privilege invasive debug enable selector set control
0 : disable
Secure privilege invasive debug disable selector set control
End of enumeration elements list.
SPNIDEN_I_SET : Secure privilege non-invasive debug enable set control
bits : 6 - 12 (7 bit)
Enumeration:
1 : enable
Secure privilege non-invasive debug enable set control
0 : disable
Secure privilege non-invasive debug disable set control
End of enumeration elements list.
SPNIDEN_SEL_SET : Secure privilege non-invasive debug enable selector set control
bits : 7 - 14 (8 bit)
Enumeration:
1 : enable
Secure privilege non-invasive debug enable selector set control
0 : disable
Secure privilege non-invasive debug disable selector set control
End of enumeration elements list.
Secure Debug Configuration Clear
address_offset : 0x8 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DBGEN_I_CLR : Debug enable clear control
bits : 0 - 0 (1 bit)
Enumeration:
1 : enable
debug enable clear control
0 : disable
debug disable clear control
End of enumeration elements list.
DBGEN_SEL_CLR : Debug enable selector clear control
bits : 1 - 2 (2 bit)
Enumeration:
1 : enable
debug enable selector clear control
0 : disable
debug disable selector clear control
End of enumeration elements list.
NIDEN_I_CLR : Non-invasive debug enable clear control
bits : 2 - 4 (3 bit)
Enumeration:
1 : enable
non-invasive debug enable clear control
0 : disable
non-invasive debug disable clear control
End of enumeration elements list.
NIDEN_SEL_CLR : Non-invasive debug enable selector clear control
bits : 3 - 6 (4 bit)
Enumeration:
1 : enable
non-invasive debug enable selector clear control
0 : disable
non-invasive debug disable selector clear control
End of enumeration elements list.
SPIDEN_I_CLR : Secure privilege invasive debug enable clear control
bits : 4 - 8 (5 bit)
Enumeration:
1 : enable
Secure privilege invasive debug enable clear control
0 : disable
Secure privilege invasive debug disable clear control
End of enumeration elements list.
SPIDEN_SEL_CLR : Secure privilege invasive debug enable selector clear control
bits : 5 - 10 (6 bit)
Enumeration:
1 : enable
Secure privilege invasive debug enable selector clear control
0 : disable
Secure privilege invasive debug disable selector clear control
End of enumeration elements list.
SPNIDEN_I_CLR : Secure privilege non-invasive debug enable clear control
bits : 6 - 12 (7 bit)
Enumeration:
1 : enable
Secure privilege non-invasive debug enable clear control
0 : disable
Secure privilege non-invasive debug disable clear control
End of enumeration elements list.
SPNIDEN_SEL_CLR : Secure privilege non-invasive debug enable selector clear control
bits : 7 - 14 (8 bit)
Enumeration:
1 : enable
Secure privilege non-invasive debug enable selector clear control
0 : disable
Secure privilege non-invasive debug disable selector clear control
End of enumeration elements list.
System Security Control
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CERTDISABLE : Control to disable certification path
bits : 0 - 0 (1 bit)
Enumeration:
1 : disable
control to disable certification path
0 : enable
control to enable certification path
End of enumeration elements list.
CERTREADEN : Control to enable read access on the certification path as long as CERTDISABLE is also LOW
bits : 1 - 2 (2 bit)
Enumeration:
1 : enable
control to enable read access on the certification path as long as CERTDISABLE is also LOW
0 : disable
control to disable read access on the certification path as long as CERTDISABLE is also LOW
End of enumeration elements list.
SCSECCFGLOCK : Control to disable writes to security-related control registers in this register block
bits : 2 - 4 (3 bit)
Enumeration:
1 : disable
control to disable writes to security-related control registers in this register block
0 : enable
control to enable writes to security-related control registers in this register block
End of enumeration elements list.
CERTDISABLED : Indicates that the Certification write path has been disabled
bits : 16 - 32 (17 bit)
Enumeration:
1 : disabled
Certification write path has been disabled
0 : enabled
Certification write path has been enabled
End of enumeration elements list.
CERTREADENABLED : Indicates whether the certification read access is enabled
bits : 17 - 34 (18 bit)
Enumeration:
1 : enabled
certification read access is enabled
0 : disabled
certification read access is disabled
End of enumeration elements list.
Peripheral ID 4
address_offset : 0xFD0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Peripheral ID 0
address_offset : 0xFE0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Peripheral ID 1
address_offset : 0xFE4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Peripheral ID 2
address_offset : 0xFE8 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Peripheral ID 3
address_offset : 0xFEC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Component ID 0
address_offset : 0xFF0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Component ID 1
address_offset : 0xFF4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Component ID 2
address_offset : 0xFF8 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Component ID 3
address_offset : 0xFFC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
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