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SAU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL

RLAR

SFSR

TYPE

RNR

RBAR


CTRL

Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE ALLNS

ENABLE : Enable
bits : 0 - 0 (1 bit)

Enumeration:

0 : Disable

SAU is disabled

1 : Enable

SAU is enabled

End of enumeration elements list.

ALLNS : Security attribution if SAU disabled
bits : 1 - 2 (2 bit)

Enumeration:

0 : Secure

Memory is marked as secure

1 : Non_Secure

Memory is marked as non-secure

End of enumeration elements list.


RLAR

Region Limit Address Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RLAR RLAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE NSC LADDR

ENABLE : SAU Region enabled
bits : 0 - 0 (1 bit)

NSC : Non-Secure Callable
bits : 1 - 2 (2 bit)

LADDR : Limit Address
bits : 5 - 36 (32 bit)


SFSR

Secure Fault Status Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SFSR SFSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INVEP INVIS INVER AUVIOL INVTRAN LSPERR SFARVALID LSERR

INVEP : Invalid entry pointd
bits : 0 - 0 (1 bit)

INVIS : Invalid integrity signature flag
bits : 1 - 2 (2 bit)

INVER : Invalid exception return flag
bits : 2 - 4 (3 bit)

AUVIOL : Attribution unit violation flag
bits : 3 - 6 (4 bit)

INVTRAN : Invalid transition flag
bits : 4 - 8 (5 bit)

LSPERR : Lazy state preservation error flag
bits : 5 - 10 (6 bit)

SFARVALID : Secure fault address valid
bits : 6 - 12 (7 bit)

LSERR : Lazy state error flag
bits : 7 - 14 (8 bit)


TYPE

Type Register
address_offset : 0x4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TYPE TYPE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SREGION

SREGION : Number of implemented SAU regions
bits : 0 - 7 (8 bit)


RNR

Region Number Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RNR RNR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REGION

REGION : Currently selected SAU region
bits : 0 - 7 (8 bit)

Enumeration:

0 : SAU_Region_0

Select SAU Region 0

1 : SAU_Region_1

Select SAU Region 1

2 : SAU_Region_2

Select SAU Region 2

3 : SAU_Region_3

Select SAU Region 3

End of enumeration elements list.


RBAR

Region Base Address Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RBAR RBAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BADDR

BADDR : Base Address
bits : 5 - 36 (32 bit)



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