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address_offset : 0x0 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected
Control Reset Register
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
GPTRESET : CPU0 interrupt status
bits : 0 - 1 (2 bit)
ALARM0 data value register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPTALARM0_DATA : Value that triggers the ALARM0 interrupt when the counter reaches that value
bits : 0 - 31 (32 bit)
GPTALARM0_DATA : Value that triggers the ALARM0 interrupt when the counter reaches that value
bits : 0 - 31 (32 bit)
GPTALARM0_DATA : Value that triggers the ALARM0 interrupt when the counter reaches that value
bits : 0 - 31 (32 bit)
GPTALARM0_DATA : Value that triggers the ALARM0 interrupt when the counter reaches that value
bits : 0 - 31 (32 bit)
GPTALARM0_DATA : Value that triggers the ALARM0 interrupt when the counter reaches that value
bits : 0 - 31 (32 bit)
ALARM1 data value register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPTALARM1_DATA : Value that triggers the ALARM1 interrupt when the counter reaches that value
bits : 0 - 31 (32 bit)
GPTALARM1_DATA : Value that triggers the ALARM1 interrupt when the counter reaches that value
bits : 0 - 31 (32 bit)
GPTALARM1_DATA : Value that triggers the ALARM1 interrupt when the counter reaches that value
bits : 0 - 31 (32 bit)
GPTALARM1_DATA : Value that triggers the ALARM1 interrupt when the counter reaches that value
bits : 0 - 31 (32 bit)
GPTALARM1_DATA : Value that triggers the ALARM1 interrupt when the counter reaches that value
bits : 0 - 31 (32 bit)
Raw interrupt status register
address_offset : 0x18 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
GPTINTR : Raw interrupt state, before masking of GPTINTR interrupt
bits : 0 - 2 (3 bit)
Counter data value register
address_offset : 0x1C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
GPTCOUNTER : Current value of 32-bit Timer Counter
bits : 0 - 31 (32 bit)
Masked interrupt status register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPTINTM : Current masked status of the interrupt
bits : 0 - 1 (2 bit)
Interrupt clear register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPTINTC : Writing 0b1 disables the ALARM[n] interrupt
bits : 0 - 1 (2 bit)
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