Cache

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

add a new register to this peripheral

ICHWPARAMS

ICIRQSTAT

ICIRQSCLR

ICIRQEN

ICDBGFILLERR

ICSH

ICSM

ICSUC

ICCTRL

PIDR4

PIDR5

PIDR6

PIDR7

PIDR0

PIDR1

PIDR2

PIDR3

CIDR0

CIDR1

CIDR2

CIDR3


ICHWPARAMS

Hardware Parameter Register
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ICHWPARAMS ICHWPARAMS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSIZE STATS DMA INVMAT COFFSIZE COFFSET

CSIZE : Cache size: Defines the size of the instruction cache
bits : 0 - 3 (4 bit)
access : read-only

STATS : Presence of Statistic Functionality
bits : 4 - 4 (1 bit)
access : read-only

DMA : Presence of DMA Engine
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

1 : Support

The Instruction cache supports pre-fetch and locking

0 : Unsupport

The Instruction cache does not support pre-fetch and locking

End of enumeration elements list.

INVMAT : Indicates whether invalidate cache line on write match is enabled
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

1 : Enabled

Indicates Invalidate Cache Line on Write Match is enabled

End of enumeration elements list.

COFFSIZE : Cacheable Block Size
bits : 12 - 15 (4 bit)
access : read-only

COFFSET : Cacheable Offset Address
bits : 16 - 31 (16 bit)
access : read-only


ICIRQSTAT

Interrupt Request Status Register
address_offset : 0x100 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ICIRQSTAT ICIRQSTAT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IC_STATUS CDC_STATUS CEC_STATUS CFE_STATUS SV_STATUS SS_STATUS

IC_STATUS : Invalidate Complete IRQ Status
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

1 : Completed

Indicates that a cache invalidation process has been completed

End of enumeration elements list.

CDC_STATUS : Cache Disable Complete IRQ Status
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

1 : Completed

Indicates that a request to disable the cache has been completed

End of enumeration elements list.

CEC_STATUS : Cache Enable Complete IRQ Status
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

1 : Completed

Indicates that a request to enable the cache has been completed

End of enumeration elements list.

CFE_STATUS : Cache Fill Error IRQ Status
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

1 : Err_Occurred

Indicates that a bus error occurred while filling a cache line

End of enumeration elements list.

SV_STATUS : Security violation IRQ Status
bits : 4 - 4 (1 bit)
access : read-only

SS_STATUS : Statistics Saturated Status
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

1 : Saturated

Indicates that the internal statistic counters have saturated

End of enumeration elements list.


ICIRQSCLR

Interrupt Status Clear register
address_offset : 0x104 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ICIRQSCLR ICIRQSCLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IC_CLR CDC_CLR CEC_CLR CFE_CLR SV_CLR SS_CLR

IC_CLR : Invalidate Complete IRQ Status Clear
bits : 0 - 0 (1 bit)
access : write-only

Enumeration:

1 : Clear

Clear the Invalidate Complete IRQ Status

End of enumeration elements list.

CDC_CLR : Cache Disable Complete IRQ Status Clear
bits : 1 - 1 (1 bit)
access : write-only

Enumeration:

1 : Clear

Clear Cache Disable Complete IRQ Status

End of enumeration elements list.

CEC_CLR : Cache Enable Complete IRQ Status Clear
bits : 2 - 2 (1 bit)
access : write-only

Enumeration:

1 : Clear

Clear the Cache Enable Complete IRQ Status

End of enumeration elements list.

CFE_CLR : Cache Fill Error IRQ Status Clear
bits : 3 - 3 (1 bit)
access : write-only

Enumeration:

1 : Clear

Clear the Cache Fill Error IRQ Status

End of enumeration elements list.

SV_CLR : Security violation IRQ Status Clear
bits : 4 - 4 (1 bit)
access : write-only

Enumeration:

1 : Clear

Clear the Security violation IRQ Status

End of enumeration elements list.

SS_CLR : Statistics Saturated Status Clear
bits : 5 - 5 (1 bit)
access : write-only

Enumeration:

1 : Clear

Clear the Statistics Saturated Status

End of enumeration elements list.


ICIRQEN

Interrupt Enable register
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICIRQEN ICIRQEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IC_EN CDC_EN CEC_EN CFE_EN SV_EN SS_EN

IC_EN : Invalidate Complete IRQ Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

1 : Enabled

Enable the Invalidate Complete IRQ

0 : Disabled

Disable the Invalidate Complete IRQ

End of enumeration elements list.

CDC_EN : Cache Disable Complete IRQ Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

1 : Enabled

Enable the Cache Disable Complete IRQ

0 : Disabled

Disable the Cache Disable Complete IRQ

End of enumeration elements list.

CEC_EN : Cache Enable Complete IRQ Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

1 : Enabled

Enable the Cache Enable Complete IRQ

0 : Disabled

Disable the Cache Enable Complete IRQ

End of enumeration elements list.

CFE_EN : Cache Fill Error IRQ Enable
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

1 : Enabled

Enable the Cache Fill Error IRQ

0 : Disabled

Disable the Cache Fill Error IRQ

End of enumeration elements list.

SV_EN : Security violation IRQ Enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

1 : Enabled

Enable the Security violation IRQ

0 : Disabled

Disable the Security violation IRQ

End of enumeration elements list.

SS_EN : Statistics Saturated Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

1 : Enabled

Enable the Statistics Saturated

0 : Disabled

Disable the Statistics Saturated

End of enumeration elements list.


ICDBGFILLERR

Address where the latest fill error was seen
address_offset : 0x10C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ICDBGFILLERR ICDBGFILLERR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ICSH

Instruction Cache Statistic Hit Count register
address_offset : 0x300 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ICSH ICSH read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ICSM

Instruction Cache Statistic Miss Count register
address_offset : 0x304 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ICSM ICSM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ICSUC

Instruction Cache Statistic Uncached Count register
address_offset : 0x308 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ICSUC ICSUC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ICCTRL

Instruction Cache Control Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICCTRL ICCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CACHEEN FINV STATEN STATC HALLOC

CACHEEN : Enable Cache
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

1 : Enabled

Caching is enabled

0 : Disabled

All accesses bypass the cache

End of enumeration elements list.

FINV : Full Cache Invalidate
bits : 2 - 2 (1 bit)
access : write-only

Enumeration:

1 : Invalidate

Triggers the instruction cache to start invalidating all cache lines

End of enumeration elements list.

STATEN : Enable Statistic function
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

1 : Enabled

Cache statistic counters are enabled

0 : Disabled

Cache statistic counters are disabled

End of enumeration elements list.

STATC : Clear Statistic values
bits : 4 - 4 (1 bit)
access : write-only

Enumeration:

1 : Clear

Triggers the instruction cache to start clear all cache statistic counters

End of enumeration elements list.

HALLOC : Enable Handler Allocation
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : LOW

All incoming handler code fetches are not allocated a cache line if a miss occurs

1 : HIGH

Handler code access is treated like any other code access arriving at its interface

End of enumeration elements list.


PIDR4

Product ID Register 4
address_offset : 0xFD0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIDR4 PIDR4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PIDR5

Product ID Register 5
address_offset : 0xFD4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIDR5 PIDR5 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PIDR6

Product ID Register 6
address_offset : 0xFD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIDR6 PIDR6 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PIDR7

Product ID Register 7
address_offset : 0xFDC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIDR7 PIDR7 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PIDR0

Product ID Register 0
address_offset : 0xFE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIDR0 PIDR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PIDR1

Product ID Register 1
address_offset : 0xFE4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIDR1 PIDR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PIDR2

Product ID Register 2
address_offset : 0xFE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIDR2 PIDR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PIDR3

Product ID Register 3
address_offset : 0xFEC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIDR3 PIDR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CIDR0

Component ID Register 0
address_offset : 0xFF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIDR0 CIDR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CIDR1

Component ID Register 1
address_offset : 0xFF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIDR1 CIDR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CIDR2

Component ID Register 2
address_offset : 0xFF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIDR2 CIDR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CIDR3

Component ID Register 3
address_offset : 0xFFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIDR3 CIDR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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