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PWM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected

Registers

PWMCR

PWMEI

PWMDI

PWMRI

PWMIS

PWMPR

PWMHR


PWMCR

PWM Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWMCR PWMCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUTPUT_SET

OUTPUT_SET : Start stop bit for the pwm_output
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

1 : Enabled

Generate programmed waveform on pwm_output

0 : Disabled

Set pwm_output continually high

End of enumeration elements list.


PWMEI

PWM Enable Interrupt Register
address_offset : 0x10 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PWMEI PWMEI write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Enable_BIT

Enable_BIT : Determines whether the write accesses the Interrupt Enable register
bits : 0 - 0 (1 bit)
access : write-only

Enumeration:

1 : Enabled

Enable the Interrupt generation

End of enumeration elements list.


PWMDI

PWM Disable Interrupt Register
address_offset : 0x14 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PWMDI PWMDI write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Disable_BIT

Disable_BIT : Determines whether the write accesses the Interrupt Disable register
bits : 0 - 0 (1 bit)
access : write-only

Enumeration:

1 : Disabled

Disable the Interrupt generation

End of enumeration elements list.


PWMRI

PWM Read Intr Enable Register.Reading from this address accesses the current state of the interrupt control registers
address_offset : 0x18 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PWMRI PWMRI read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Enable_BIT

Enable_BIT : Check whether the Interrupt is Enabled
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

1 : Enabled

Interrupt is Enabled

End of enumeration elements list.


PWMIS

PWM Read Interrupt Status Register
address_offset : 0x1C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PWMIS PWMIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Status

Status : Reading from this address returns the current state of the PWM Interrupt output, and then sets the bit low
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

1 : Active

Interrupt is active

0 : Not active

Interrupt is not active

End of enumeration elements list.


PWMPR

PWM Period Register. Number of system clock cycles indicating the period of PWM cycle.The minimum and maximum values have special significance. 0x0: pwm_output continually high 0xFFFFFFFF: pwm_output continually low
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWMPR PWMPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PWMHR

PWM High Iime Register. This register contains the number of system clock cycles for during which the pwm_output should be kept high in a PWM cycle
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWMHR PWMHR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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