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SPI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xFC byte (0x0)
mem_usage : registers
protection : not protected

Registers

SPICR

SPIIMR

SPIENR

SPITDR

SPIRDR

SPIISR

SPIIER

SPIIDR


SPICR

Control register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPICR SPICR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSEL CPOL CPHA MBRD TWS MRCS PSD PCSL MCSE MSE MSC MFGE SPSE RXCLR TXCLR

MSEL : Mode Select: Selects SPI controller mode (MASTER/SLAVE)
bits : 0 - 0 (1 bit)

CPOL : External Clock Edge: Selects the SPI clock polarity outside SPI word
bits : 1 - 1 (1 bit)

CPHA : Clock Phase: Selects whether the SPI clock is in active or inactive phase outside the SPI word
bits : 2 - 2 (1 bit)

MBRD : Master Baud Rate Divisor (2 to 256). The SCLK is generated base on SPI REFERENCE CLOCK or ext_clk divided by MBRD
bits : 3 - 5 (3 bit)

TWS : Transfer Word Size: Define size of word to be transferred. This MUST be equal to the FIFO width (FF_W), or a sub-multiple of FF_W to allow multiple word transfers per FIFO word
bits : 6 - 7 (2 bit)

MRCS : Reference Clock Select: When this bit is set the ext_clk is used, otherwise SPI REFERENCE CLOCK is used
bits : 8 - 8 (1 bit)

PSD : Peripheral Select Decode: When this bit is set allow external 4-to-16 decode (n_ss_out [3:0 = PCSL [3:0]). When Peripheral Select Decode is not set, only 1 of 4 selects n_ss_out[3:0] are active (see PCSL)
bits : 9 - 9 (1 bit)

PCSL : Peripheral Chip Select Lines (master mode only): When Peripheral Select Decode is set then PCSL[3:0] directly drives n_ss_out [3:0], else (PSD is written with ‘0’) PCSL[3:0] drives n_ss_out [3:0]
bits : 10 - 13 (4 bit)

MCSE : Manual Chip Select Enable: When this bit is set, the n_ss_out[3:0] lines will be driven permanently by the encoded peripheral select value regardless of the current state of the main SPI state machine
bits : 14 - 14 (1 bit)

MSE : Manual Start Enable: When this bit is set do not allow transmission to start until Manual Start Command (see MSC) bit is written with a '1'
bits : 15 - 15 (1 bit)

MSC : Manual Start Command: When manual start mode is enabled (see Manual Start Enable bit of Configuration Register) and TX FIFO is not empty, writing a ‘1’ to this bit will start transmission. Writing a '0' will have no effect. It returns ‘0’ when read
bits : 16 - 16 (1 bit)

MFGE : Mode Fail Generation Enable: When this bit is set the logic generating Mode Fail is enabled
bits : 17 - 17 (1 bit)

SPSE : Sample Point Shift Enable: When this bit is set and controller is in MASTER receiver mode then sample point of receiving data is shifted with respect to sample point of SPI protocol specification
bits : 18 - 18 (1 bit)

RXCLR : RX FIFO Clear: Writing a ‘1’ to this bit will clear the RX FIFO. Writing a '0' will have no effect. It returns ‘0’ when read
bits : 19 - 19 (1 bit)

TXCLR : TX FIFO Clear: Writing a ‘1’ to this bit will clear the TX FIFO. Writing a '0' will have no effect. It returns ‘0’ when read
bits : 20 - 20 (1 bit)


SPIIMR

Interrupt Mask Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SPIIMR SPIIMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ROFM MFM TNFM TFM RNEM RFM TUFM

ROFM : RX FIFO Overflow Mask
bits : 0 - 0 (1 bit)

MFM : Mode Fail Mask
bits : 1 - 1 (1 bit)

TNFM : TX FIFO Not Full Mask
bits : 2 - 2 (1 bit)

TFM : TX FIFO Full Mask
bits : 3 - 3 (1 bit)

RNEM : RX FIFO Not Empty Mask
bits : 4 - 4 (1 bit)

RFM : RX FIFO Full Mask
bits : 5 - 5 (1 bit)

TUFM : TX FIFO Underflow Mask
bits : 6 - 6 (1 bit)


SPIENR

SPI Enable Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPIENR SPIENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPIE

SPIE : SPI Enable: When this bit is set the SPI controller is enabled, otherwise SPI is disabled. When SPI controller is disabled all output enables are inactive and all pins are set to input mode. Writing ‘0’ disables the SPI controller once current transfer of the data word (FF_W) is complete
bits : 0 - 0 (1 bit)


SPITDR

Transmit Data Register
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SPITDR SPITDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TDATA

TDATA : Transmit Data: Writes to the TX FIFO location indicated by its internal write address and increments the write address by pushing it
bits : 0 - 7 (8 bit)


SPIRDR

Receive Data Register
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SPIRDR SPIRDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDATA

RDATA : Receive Data: Reads the RX FIFO location indicated by the current read address and then increments the read address
bits : 0 - 7 (8 bit)


SPIISR

Interrupt Status Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SPIISR SPIISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ROF MF TNF TF RNE RF TUF

ROF : RX FIFO Overflow: This bit is set if an attempt is made to push the RX FIFO when it is full
bits : 0 - 0 (1 bit)

MF : Mode Fail: Indicates the voltage on pin n_ss_in is inconsistent with the SPI mode
bits : 1 - 1 (1 bit)

TNF : TX FIFO Not Full (current FIFO status)
bits : 2 - 2 (1 bit)

TF : TX FIFO Full (current FIFO status)
bits : 3 - 3 (1 bit)

RNE : RX FIFO Not Empty (current FIFO status)
bits : 4 - 4 (1 bit)

RF : RX FIFO Full (current FIFO status)
bits : 5 - 5 (1 bit)

TUF : TX FIFO Underflow: This bit is reset only by a system reset and cleared only when the register is read
bits : 6 - 6 (1 bit)


SPIIER

Interrupt Enable Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SPIIER SPIIER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ROFE MFE TNFE TFE RNEE RFE TUFE

ROFE : RX FIFO Overflow Enable
bits : 0 - 0 (1 bit)

MFE : Mode Fail Enable
bits : 1 - 1 (1 bit)

TNFE : TX FIFO Not Full Enable
bits : 2 - 2 (1 bit)

TFE : TX FIFO Full Enable
bits : 3 - 3 (1 bit)

RNEE : RX FIFO Not Empty Enable
bits : 4 - 4 (1 bit)

RFE : RX FIFO Full Enable
bits : 5 - 5 (1 bit)

TUFE : TX FIFO Underflow Enable
bits : 6 - 6 (1 bit)


SPIIDR

Interrupt Disable Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SPIIDR SPIIDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ROFD MFD TNFD TFD RNED RFD TUFD

ROFD : RX FIFO Overflow Disable
bits : 0 - 0 (1 bit)

MFD : Mode Fail Disable
bits : 1 - 1 (1 bit)

TNFD : TX FIFO Not Full Disable
bits : 2 - 2 (1 bit)

TFD : TX FIFO Full Disable
bits : 3 - 3 (1 bit)

RNED : RX FIFO Not Empty Disable
bits : 4 - 4 (1 bit)

RFD : RX FIFO Full Disable
bits : 5 - 5 (1 bit)

TUFD : TX FIFO Underflow Disable
bits : 6 - 6 (1 bit)



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