\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
sel_premux_clk : 0: 32k 1: FASTCLK
bits : 0 - 0 (1 bit)
sel_dapswmux_clk : 0: PRE_MUX_CLK 1: TCK
bits : 1 - 2 (2 bit)
sel_mainmux_clk : 0: PLL0_CLK 1: PRE_MUX_CLK
bits : 2 - 4 (3 bit)
sel_refmux_clk : 0: PRE_MUX_CLK 1: PRE_PLL_CLK
bits : 3 - 6 (4 bit)
sel_rm38kmux_clk : 0: REF_MUX_CLK 1: RM38K
bits : 4 - 8 (5 bit)
sel_sccmux_clk : 0: SCCCLK 1: PRE_MUX_CLK
bits : 5 - 10 (6 bit)
sel_rm38p4_premux_clk : 0: SYSSYSSUGCLK 1: NRM138P4
bits : 6 - 12 (7 bit)
ctrl_sel_test_mux_clk : ctrl_sel_test_mux_clk
bits : 7 - 18 (12 bit)
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
postdiv_ctrl_qspi_div : postdiv_ctrl_qspi_div
bits : 0 - 7 (8 bit)
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
pull_select : Enables pull resistors of test chip I/O PA31-PA0
bits : 0 - 31 (32 bit)
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
pull_select : Enables pull resistors of test chip I/O PA37-PA32
bits : 0 - 5 (6 bit)
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
slew_rate : Selects the slew rate of test chip I/O PA31-PA0
bits : 0 - 31 (32 bit)
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
slew_rate : Selects the slew rate of test chip I/O PA37-PA32
bits : 0 - 5 (6 bit)
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
input_select : Selects input mode on test chip I/O PA31-PA0
bits : 0 - 31 (32 bit)
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
input_select : Selects input mode on test chip I/O PA37-PA32
bits : 0 - 5 (6 bit)
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSTSENNUM : Select PVT sensor to write to and read from
bits : 0 - 4 (5 bit)
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
spare0 : Spare read-write register for software
bits : 0 - 31 (32 bit)
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TISBYPASSIN : Cross Trigger Interface synchronous bypass on CTITRIGIN
bits : 0 - 7 (8 bit)
TISBYPASSACK : Cross Trigger Interface synchronous bypass on CTITRIGOUTACK
bits : 8 - 19 (12 bit)
TIHSBYPASS : Cross Trigger Interface handshake bypass on CTITRIGOUT
bits : 12 - 27 (16 bit)
TINIDENSEL : NIDEN mask on CTITRIGINT
bits : 16 - 39 (24 bit)
TODBGENSEL : DBGEN mask on CTITRIGOUT
bits : 24 - 51 (28 bit)
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
postdiv_ctrl_rtc_div : postdiv_ctrl_rtc_div
bits : 0 - 31 (32 bit)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
postdiv_ctrl_sd_div : postdiv_ctrl_sd_div
bits : 0 - 7 (8 bit)
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
scc_flash_din0 : eFlash 0 and eFlash 1 data input[31:0]
bits : 0 - 31 (32 bit)
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
scc_flash_din1 : eFlash 0 and eFlash 1 data input{63:32]
bits : 0 - 31 (32 bit)
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
scc_flash_din2 : eFlash 0 and eFlash 1 data input[95:64]
bits : 0 - 31 (32 bit)
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
scc_flash_din3 : eFlash 0 and eFlash 1 data input[127:96]
bits : 0 - 31 (32 bit)
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
postdiv_ctrl_test_div : postdiv_ctrl_test_div
bits : 0 - 7 (8 bit)
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
scc_flash0_dout0 : eFlash 0 data output[31:0]
bits : 0 - 31 (32 bit)
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
scc_flash0_dout1 : eFlash 0 data output[63:32]
bits : 0 - 31 (32 bit)
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
scc_flash0_dout2 : eFlash 0 data output[95:64]
bits : 0 - 31 (32 bit)
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
scc_flash0_dout3 : eFlash 0 data output[127:96]
bits : 0 - 31 (32 bit)
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
scc_flash1_dout0 : eFlash 1 data output[31:0]
bits : 0 - 31 (32 bit)
address_offset : 0x1D4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
scc_flash1_dout1 : eFlash 1 data output[63:32]
bits : 0 - 31 (32 bit)
address_offset : 0x1D8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
scc_flash1_dout2 : eFlash 1 data output[95:64]
bits : 0 - 31 (32 bit)
address_offset : 0x1DC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
scc_flash1_dout3 : eFlash 1 data output[127:96]
bits : 0 - 31 (32 bit)
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
clock_phase_shifter_select : QSPI input clock phase shift control
bits : 0 - 1 (2 bit)
clock_phase_shifter_bypass : QSPI input clock phase shift control
bits : 2 - 4 (3 bit)
sdio_mask_delay : SDIO mask delay
bits : 8 - 17 (10 bit)
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
az_rom_remap_mask : Alcatraz ROM remap mask
bits : 0 - 31 (32 bit)
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
az_rom_remap_offset : Alcatraz ROM remap offset
bits : 0 - 31 (32 bit)
address_offset : 0x1EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
az_code_remap_mask : Alcatraz code remap mask
bits : 0 - 31 (32 bit)
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
az_code_remap_offset : Alcatraz code remap offset
bits : 0 - 31 (32 bit)
address_offset : 0x1F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
az_sys_remap_mask : Alcatraz system remap mask
bits : 0 - 31 (32 bit)
address_offset : 0x1F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
az_sys_remap_offset : Alcatraz system remap offset
bits : 0 - 31 (32 bit)
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
bypass_div_pll_div_prediv_clk : 0: Not bypass 1: bypass
bits : 0 - 0 (1 bit)
bypass_qspi_div_clk : 0: Not bypass 1: bypass
bits : 3 - 6 (4 bit)
bypass_rtc_div_clk : 0: Not bypass 1: bypass
bits : 4 - 8 (5 bit)
bypass_sd_div_clk : 0: Not bypass 1: bypass
bits : 5 - 10 (6 bit)
bypass_test_div_clk : 0: Not bypass 1: bypass
bits : 6 - 12 (7 bit)
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AZ_BOOT_REMAP : Alcatraz remap at boot
bits : 0 - 0 (1 bit)
CPUWAIT : Alcatraz CPU wait at boot:
bits : 1 - 2 (2 bit)
REMOVE_CHACHA_ENGINE : Alcatraz CryptoCell remove CHACHA engine
bits : 2 - 4 (3 bit)
REMOVE_GHASH_ENGINE : Alcatraz CryptoCell remove Ghash engine
bits : 3 - 6 (4 bit)
CHSEC_ISO_ENB : Alcatraz CryptoCell Secure Frame Isolation enable
bits : 4 - 8 (5 bit)
CHSEC_MISC_7 : Alcatraz CryptoCell secure Secure Frame control
bits : 5 - 10 (6 bit)
DBGRESETn : Alcatraz reset DBGRESETn
bits : 7 - 14 (8 bit)
HRESETn : Alcatraz reset HRESETn
bits : 8 - 16 (9 bit)
SCC_nPORESETAON_nPORESET_SEL : Alcatraz reset control
bits : 9 - 18 (10 bit)
SCC_PSI_FEATURE_EN : Value of SCC_PSI_FEATURE_EN from SCC
bits : 10 - 20 (11 bit)
SCC_PSI_FEATURE_EN_SEL : Select PSI_FEATURE_EN source
bits : 11 - 22 (12 bit)
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
sse_otp_rd_data : SSE-200 OTP read data
bits : 0 - 31 (32 bit)
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
az_otp_rd_data : Alcatraz OTP read data
bits : 0 - 31 (32 bit)
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
spare_ctrl0 : Spare control register
bits : 0 - 31 (32 bit)
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
spare_ctrl1 : Spare control register
bits : 0 - 31 (32 bit)
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
pd_pll0 : Power down PLL0
bits : 0 - 0 (1 bit)
pd_foutpostdiv1pd : Power down FOUTPOSTDIV1PD:
bits : 1 - 2 (2 bit)
pd_foutpostdiv2pd : Power down FOUTPOSTDIV2PD
bits : 2 - 4 (3 bit)
pd_foutvcopd : Power down FOUTVCOPD
bits : 3 - 6 (4 bit)
bypass_pll0 : Bypass PLL0
bits : 4 - 8 (5 bit)
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
pll_postdiv_ctrl_pll0_clk : pll_postdiv_ctrl_pll0_clk
bits : 0 - 3 (4 bit)
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
pll_mult_ctrl_pll0_clk : pll_mult_ctrl_pll0_clk
bits : 0 - 13 (14 bit)
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ctrl_enable_1hz : 0: Disable 1: Enable
bits : 0 - 0 (1 bit)
ctrl_enable_dapswclk : 0: Disable 1: Enable
bits : 1 - 2 (2 bit)
ctrl_enable_gpiohclk : 0: Disable 1: Enable
bits : 2 - 4 (3 bit)
ctrl_enable_i2sclk0 : 0: Disable 1: Enable
bits : 3 - 6 (4 bit)
ctrl_enable_i2sclk1 : 0: Disable 1: Enable
bits : 4 - 8 (5 bit)
ctrl_enable_i2sclk2 : 0: Disable 1: Enable
bits : 5 - 10 (6 bit)
ctrl_enable_mainclk : 0: Disable 1: Enable
bits : 8 - 16 (9 bit)
ctrl_enable_qspi_phy_clk : 0: Disable 1: Enable
bits : 9 - 18 (10 bit)
ctrl_enable_refclk : 0: Disable 1: Enable
bits : 10 - 20 (11 bit)
ctrl_enable_rm38kclk : 0: Disable 1: Enable
bits : 11 - 22 (12 bit)
ctrl_enable_sccclk : 0: Disable 1: Enable
bits : 12 - 24 (13 bit)
ctrl_enable_sdphyclk : 0: Disable 1: Enable
bits : 13 - 26 (14 bit)
ctrl_enable_testclk : 0: Disable 1: Enable
bits : 15 - 30 (16 bit)
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
status_out_clk_mainclk_ready : Clock ready (active)
bits : 0 - 0 (1 bit)
status_lock_signal_pll0_clk : PLL Lock Status
bits : 1 - 2 (2 bit)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
prediv_ctrl : prediv_ctrl
bits : 0 - 9 (10 bit)
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPTIMER_RESET : Reset Active low
bits : 1 - 2 (2 bit)
I2C0_RESET : Reset Active low
bits : 2 - 4 (3 bit)
I2C1_RESET : Reset Active low
bits : 3 - 6 (4 bit)
I2S_RESET : Reset Active low
bits : 4 - 8 (5 bit)
SPI_RESET : Reset Active low
bits : 5 - 10 (6 bit)
QSPI_RESET : Reset Active low
bits : 6 - 12 (7 bit)
UART0_RESET : Reset Active low
bits : 7 - 14 (8 bit)
UART1_RESET : Reset Active low
bits : 8 - 16 (9 bit)
GPIO_RESET : Reset Active low
bits : 9 - 18 (10 bit)
PVT_RESET : Reset Active low
bits : 10 - 20 (11 bit)
PWM0_RESET : Reset Active low
bits : 11 - 22 (12 bit)
PWM1_RESET : Reset Active low
bits : 12 - 24 (13 bit)
PWM2_RESET : Reset Active low
bits : 13 - 26 (14 bit)
RTC_RESET : Reset Active low
bits : 14 - 28 (15 bit)
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
chip_id : Component ID information
bits : 0 - 31 (32 bit)
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSE_200_DBGENIN : 0: Not enable 1: Enable
bits : 0 - 0 (1 bit)
SSE_200_NIDENIN : 0: Not enable 1: Enable
bits : 1 - 2 (2 bit)
SSE_200_SPIDENIN : 0: Not enable 1: Enable
bits : 2 - 4 (3 bit)
SSE_200_SPNIDENIN : 0: Not enable 1: Enable
bits : 3 - 6 (4 bit)
TODBGENSEL0 : 0: Enable 1: Mask or bypass
bits : 7 - 14 (8 bit)
TODBGENSEL1 : 0: Enable 1: Mask or bypass
bits : 8 - 16 (9 bit)
DBG_DCU_FORCE : SSE-200 debug ports control
bits : 30 - 61 (32 bit)
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CODE_SRAMx_PGEN : SRAM cell power gate enable
bits : 0 - 15 (16 bit)
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QSPI_MPC_CFG_INIT_VALUE : 0: Secure mode 1: Non-secure mode
bits : 3 - 6 (4 bit)
SRAM_MPC_CFG_INIT_VALUE : 0: Secure mode 1: Non-secure mode
bits : 5 - 10 (6 bit)
AZ_MPC_CFG_INIT_VALUE : 0: Secure mode 1: Non-secure mode
bits : 6 - 12 (7 bit)
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLK_TEST_SEL : Select TESTMUX input
bits : 0 - 4 (5 bit)
CLK_TEST_EN : 0: Not enable 1: Enable
bits : 5 - 10 (6 bit)
CLK_MAIN_FORCE_RDY : CLK_MAIN_FORCE_RDY
bits : 6 - 12 (7 bit)
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU0_VTOR_SECURE : Reset vector for CPU0 secure mode
bits : 7 - 38 (32 bit)
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU1_VTOR_SECURE : Reset vector for CPU1 secure mode
bits : 7 - 38 (32 bit)
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AZ_ROM_REMAP : Remap vector for Alcatraz ROM address space.
bits : 0 - 7 (8 bit)
AZ_CODE_REMAP : Remap vector for Alcatraz Code address space
bits : 8 - 23 (16 bit)
AZ_SYS_REMAP : Remap vector for Alcatraz System address space
bits : 16 - 39 (24 bit)
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
iomux_main_insel_0 : 0: Select ATF1 1: Select Main Function
bits : 0 - 31 (32 bit)
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
iomux_main_insel_1 : 0: Select ATF1 1: Select Main Function
bits : 0 - 5 (6 bit)
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
iomux_main_outsel_0 : 0: Select ATF1 1: Select Main Function
bits : 0 - 31 (32 bit)
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
iomux_main_outsel_1 : 0: Select ATF1 1: Select Main Function
bits : 0 - 5 (6 bit)
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
iomux_main_oensel_0 : 0: Select ATF1 1: Select Main Function
bits : 0 - 31 (32 bit)
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
iomux_main_oensel_1 : 0: Select ATF1 1: Select Main Function
bits : 0 - 5 (6 bit)
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
iomux_main_default_in_0 : 0: Default to 0 1: Default to 1
bits : 0 - 31 (32 bit)
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
iomux_main_default_in_1 : 0: Default to 0 1: Default to 1
bits : 0 - 5 (6 bit)
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
iomux_altf1_insel_0 : 0: Select ATF2 1: Select ATF1
bits : 0 - 31 (32 bit)
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
iomux_altf1_insel_1 : 0: Select ATF2 1: Select ATF1
bits : 0 - 5 (6 bit)
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
iomux_altf1_outsel_0 : 0: Select ATF2 1: Select ATF1
bits : 0 - 31 (32 bit)
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
iomux_altf1_outsel_1 : 0: Select ATF2 1: Select ATF1
bits : 0 - 5 (6 bit)
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
iomux_altf1_oensel_0 : 0: Select ATF2 1: Select ATF1
bits : 0 - 31 (32 bit)
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
iomux_altf1_oensel_1 : 0: Select ATF2 1: Select ATF1
bits : 0 - 5 (6 bit)
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
iomux_altf1_default_in_0 : 0: Default to 0 1: Default to 1
bits : 0 - 31 (32 bit)
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
iomux_altf1_default_in_1 : 0: Default to 0 1: Default to 1
bits : 0 - 5 (6 bit)
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
iomux_altf2_insel_0 : 0: Select ATF3 1: Select ATF2
bits : 0 - 31 (32 bit)
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
iomux_altf2_insel_1 : 0: Select ATF3 1: Select ATF2
bits : 0 - 5 (6 bit)
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
iomux_altf2_outsel_0 : 0: Select ATF3 1: Select ATF2
bits : 0 - 31 (32 bit)
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
iomux_altf2_outsel_1 : 0: Select ATF3 1: Select ATF2
bits : 0 - 5 (6 bit)
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
iomux_altf2_oensel_0 : 0: Select ATF3 1: Select ATF2
bits : 0 - 31 (32 bit)
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
iomux_altf2_oensel_1 : 0: Select ATF3 1: Select ATF2
bits : 0 - 5 (6 bit)
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
postdiv_ctrl_flash_div : postdiv_ctrl_flash_div
bits : 0 - 7 (8 bit)
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
iomux_altf2_default_in_0 : 0: Default to 0 1: Default to 1
bits : 0 - 31 (32 bit)
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
iomux_altf2_default_in_1 : 0: Default to 0 1: Default to 1
bits : 0 - 5 (6 bit)
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
drive_strength0 : Least significant bits of the two-bit values that define drive strengths of test chip I/O PA31-PA0
bits : 0 - 31 (32 bit)
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
drive_strength_0 : Least significant bits of the two-bit values that define drive strengths of test chip I/O PA37-PA32
bits : 0 - 5 (6 bit)
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
drive_strength1 : Most significant bits of the two-bit values that define drive strengths of test chip I/O PA31-PA0
bits : 0 - 31 (32 bit)
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
drive_strength_1 : Most significant bits of the two-bit values that define drive strengths of test chip I/O PA37-PA32
bits : 0 - 5 (6 bit)
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
pull_enable : Enables pull resistors of test chip I/O PA31-PA0
bits : 0 - 31 (32 bit)
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
pull_enable : Enables pull resistors of test chip I/O PA37-PA32
bits : 0 - 5 (6 bit)
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