Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x4C byte (0x0)
mem_usage : registers
protection : not protected
Data Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Data : Receive/Transmit data
bits : 0 - 7 (8 bit)
FE : Framing error: Indicates the received character did not had a valid stop bit
bits : 8 - 16 (9 bit)
PE : Parity error: Indicates that the parity of the received data character does not match the parity selected
bits : 9 - 18 (10 bit)
BE : Break error: Indicates that the received data input was held LOW for longer than a full-word transmission time
bits : 10 - 20 (11 bit)
OE : Overrun error: Indicates if data is received and the receive FIFO is already full
bits : 11 - 22 (12 bit)
Flag Register
address_offset : 0x18 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CTS : Clear to send
bits : 0 - 0 (1 bit)
DSR : Data set ready
bits : 1 - 2 (2 bit)
DCD : Data carrier detect
bits : 2 - 4 (3 bit)
BUSY : UART busy
bits : 3 - 6 (4 bit)
RXFE : Receive FIFO empty
bits : 4 - 8 (5 bit)
TXFF : Transmit FIFO full
bits : 5 - 10 (6 bit)
RXFF : Receive FIFO full
bits : 6 - 12 (7 bit)
TXFE : Transmit FIFO empty
bits : 7 - 14 (8 bit)
RI : Ring indicator
bits : 8 - 16 (9 bit)
IrDA low-power counter Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ILPDVSR : 8-bit low-power divisor value
bits : 0 - 7 (8 bit)
Integer baud rate Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BAUD_DIVINT : The integer baud rate divisor
bits : 0 - 15 (16 bit)
Fractional baud rate Register
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BAUD_DIVINT : The integer baud rate divisor
bits : 0 - 5 (6 bit)
Line control Register
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRK : Send break
bits : 0 - 0 (1 bit)
PEN : Parity enable
bits : 1 - 2 (2 bit)
EPS : Even parity select
bits : 2 - 4 (3 bit)
STP2 : Two stop bits select
bits : 3 - 6 (4 bit)
FEN : Enable FIFOs
bits : 4 - 8 (5 bit)
WLEN : Word length
bits : 5 - 11 (7 bit)
SPS : Stick parity select
bits : 7 - 14 (8 bit)
Control Register
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UARTEN : UART enable
bits : 0 - 0 (1 bit)
Enumeration:
0 : Disable
UART is disabled
1 : Enable
UART is enabled
End of enumeration elements list.
SIREN : SIR enable
bits : 1 - 2 (2 bit)
Enumeration:
0 : Disable
SIR is disabled
1 : Enable
SIR is enabled
End of enumeration elements list.
SIRLP : IrDA SIR low power mode
bits : 2 - 4 (3 bit)
Enumeration:
0 : Disable
SIR low power mode is disabled
1 : Enable
SIR low power mode is enabled
End of enumeration elements list.
LBE : Loop back enable
bits : 7 - 14 (8 bit)
Enumeration:
0 : Disable
Loop back mode is disabled
1 : Enable
Loop back mode is enabled
End of enumeration elements list.
TXE : Transmit enable
bits : 8 - 16 (9 bit)
Enumeration:
0 : Disable
Transmission is disabled
1 : Enable
Transmission is enabled
End of enumeration elements list.
RXE : Receive enable
bits : 9 - 18 (10 bit)
Enumeration:
0 : Disable
Reception is disabled
1 : Enable
Reception is enabled
End of enumeration elements list.
DTR : Data transmit ready
bits : 10 - 20 (11 bit)
RTS : Request to send
bits : 11 - 22 (12 bit)
Out1 : Complement of the UART Out1
bits : 12 - 24 (13 bit)
Out2 : Complement of the UART Out2
bits : 13 - 26 (14 bit)
RTSEn : RTS hardware flow control enable
bits : 14 - 28 (15 bit)
Enumeration:
0 : Disable
RTS hardware flow control is disabled
1 : Enable
RTS hardware flow control is enabled
End of enumeration elements list.
CTSEn : CTS hardware flow control enable
bits : 15 - 30 (16 bit)
Enumeration:
0 : Disable
CTS hardware flow control is disabled
1 : Enable
CTS hardware flow control is enabled
End of enumeration elements list.
Interrupt FIFO level select Register
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXIFLSEL : Transmit interrupt FIFO level select
bits : 0 - 2 (3 bit)
Enumeration:
0 : 1/8 full
Transmit FIFO becomes less than or equal to 1/8 full
1 : 1/4 full
Transmit FIFO becomes less than or equal to 1/4 full
2 : 1/2 full
Transmit FIFO becomes less than or equal to 1/2 full
3 : 3/4 full
Transmit FIFO becomes less than or equal to 3/4 full
4 : 7/8 full
Transmit FIFO becomes less than or equal to 7/8 full
End of enumeration elements list.
RXIFLSEL : Receive interrupt FIFO level select
bits : 3 - 8 (6 bit)
Enumeration:
0 : 1/8 full
Receive FIFO becomes greater than or equal to 1/8 full
1 : 1/4 full
Receive FIFO becomes greater than or equal to 1/4 full
2 : 1/2 full
Receive FIFO becomes greater than or equal to 1/2 full
3 : 3/4 full
Receive FIFO becomes greater than or equal to 3/4 full
4 : 7/8 full
Receive FIFO becomes greater than or equal to 7/8 full
End of enumeration elements list.
Interrupt mask set/clear Register
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RIMIM : nUARTRI modem interrupt mask
bits : 0 - 0 (1 bit)
Enumeration:
0 : Clear
Clears the mask
1 : Set
Sets the mask
End of enumeration elements list.
CTSMIM : nUARTCTS modem interrupt mask
bits : 1 - 2 (2 bit)
Enumeration:
0 : Clear
Clears the mask
1 : Set
Sets the mask
End of enumeration elements list.
DCDMIM : nUARTDCD modem interrupt mask
bits : 2 - 4 (3 bit)
Enumeration:
0 : Clear
Clears the mask
1 : Set
Sets the mask
End of enumeration elements list.
DSRMIM : nUARTDSR modem interrupt mask
bits : 3 - 6 (4 bit)
Enumeration:
0 : Clear
Clears the mask
1 : Set
Sets the mask
End of enumeration elements list.
RXIM : Receive interrupt mask
bits : 4 - 8 (5 bit)
Enumeration:
0 : Clear
Clears the mask
1 : Set
Sets the mask
End of enumeration elements list.
TXIM : Transmit interrupt mask
bits : 5 - 10 (6 bit)
Enumeration:
0 : Clear
Clears the mask
1 : Set
Sets the mask
End of enumeration elements list.
RTIM : Receive timeout interrupt mask
bits : 6 - 12 (7 bit)
Enumeration:
0 : Clear
Clears the mask
1 : Set
Sets the mask
End of enumeration elements list.
FEIM : Framing error interrupt mask
bits : 7 - 14 (8 bit)
Enumeration:
0 : Clear
Clears the mask
1 : Set
Sets the mask
End of enumeration elements list.
PEIM : Parity error interrupt mask
bits : 8 - 16 (9 bit)
Enumeration:
0 : Clear
Clears the mask
1 : Set
Sets the mask
End of enumeration elements list.
BEIM : Break error interrupt mask
bits : 9 - 18 (10 bit)
Enumeration:
0 : Clear
Clears the mask
1 : Set
Sets the mask
End of enumeration elements list.
OEIM : Overrun error interrupt mask
bits : 10 - 20 (11 bit)
Enumeration:
0 : Clear
Clears the mask
1 : Set
Sets the mask
End of enumeration elements list.
Raw interrupt status Register
address_offset : 0x3C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RIRMIS : nUARTRI modem interrupt status
bits : 0 - 0 (1 bit)
CTSRMIS : nUARTCTS modem interrupt status
bits : 1 - 1 (1 bit)
DCDRMIS : nUARTDCD modem interrupt status
bits : 2 - 2 (1 bit)
DSRRMIS : nUARTDSR modem interrupt status
bits : 3 - 3 (1 bit)
RXRIS : Receive interrupt status
bits : 4 - 4 (1 bit)
TXRIS : Transmit interrupt status
bits : 5 - 5 (1 bit)
RTRIS : Receive timeout interrupt status
bits : 6 - 6 (1 bit)
FERIS : Framing error interrupt status
bits : 7 - 7 (1 bit)
PERIS : Parity error interrupt status
bits : 8 - 8 (1 bit)
BERIS : Break error interrupt status
bits : 9 - 9 (1 bit)
OERIS : Overrun error interrupt status
bits : 10 - 10 (1 bit)
Receive status register/error clear Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : UARTECR
reset_Mask : 0x0
FE : Framing error: Indicates the received character did not had a valid stop bit
bits : 0 - 0 (1 bit)
PE : Parity error: Indicates that the parity of the received data character does not match the parity selected
bits : 1 - 2 (2 bit)
BE : Break error: Indicates that the received data input was held LOW for longer than a full-word transmission time
bits : 2 - 4 (3 bit)
OE : Overrunerror: Indicates if data is received and the receive FIFO is already full
bits : 3 - 6 (4 bit)
Masked interrupt status Register
address_offset : 0x40 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RIMMIS : nUARTRI modem masked interrupt status
bits : 0 - 0 (1 bit)
CTSMMIS : nUARTCTS modem masked interrupt status
bits : 1 - 1 (1 bit)
DCDMMIS : nUARTDCD modem masked interrupt status
bits : 2 - 2 (1 bit)
DSRMMIS : nUARTDSR modem masked interrupt status
bits : 3 - 3 (1 bit)
RXMIS : Receive masked interrupt status
bits : 4 - 4 (1 bit)
TXMIS : Transmit masked interrupt status
bits : 5 - 5 (1 bit)
RTMIS : Receive timeout masked interrupt status
bits : 6 - 6 (1 bit)
FEMIS : Framing error masked interrupt status
bits : 7 - 7 (1 bit)
PEMIS : Parity error masked interrupt status
bits : 8 - 8 (1 bit)
BEMIS : Break error masked interrupt status
bits : 9 - 9 (1 bit)
OEMIS : Overrun error masked interrupt status
bits : 10 - 10 (1 bit)
Interrupt clear Register
address_offset : 0x44 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RIMIC : nUARTRI modem interrupt clear, write 1 to clear, write 0 has no effect
bits : 0 - 0 (1 bit)
CTSMIC : nUARTCTS modem interrupt clear, write 1 to clear, write 0 has no effect
bits : 1 - 1 (1 bit)
DCDMIC : nUARTDCD modem interrupt clear, write 1 to clear, write 0 has no effect
bits : 2 - 2 (1 bit)
DSRIC : nUARTDSR modem interrupt clear, write 1 to clear, write 0 has no effect
bits : 3 - 3 (1 bit)
RXIC : Receive interrupt clear, write 1 to clear, write 0 has no effect
bits : 4 - 4 (1 bit)
TXIC : Transmit interrupt clear, write 1 to clear, write 0 has no effect
bits : 5 - 5 (1 bit)
RTIC : Receive timeout interrupt clear, write 1 to clear, write 0 has no effect
bits : 6 - 6 (1 bit)
FEIC : Framing error interrupt clear, write 1 to clear, write 0 has no effect
bits : 7 - 7 (1 bit)
PEIC : Parity error interrupt clear, write 1 to clear, write 0 has no effect
bits : 8 - 8 (1 bit)
BEIC : Break error interrupt clear, write 1 to clear, write 0 has no effect
bits : 9 - 9 (1 bit)
OEIC : Overrun error interrupt clear, write 1 to clear, write 0 has no effect
bits : 10 - 10 (1 bit)
DMA control Register
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXDMAE : Receive DMA enable
bits : 0 - 0 (1 bit)
Enumeration:
0 : Disable
Receive DMA is disabled
1 : Enable
Receive DMA is enabled
End of enumeration elements list.
TXDMAE : Transmit DMA enable
bits : 1 - 1 (1 bit)
Enumeration:
0 : Disable
Transmit DMA is disabled
1 : Enable
Transmit DMA is enabled
End of enumeration elements list.
DMAONERR : DMA on error
bits : 2 - 4 (3 bit)
Enumeration:
0 : Disable
DMA receive request outputs are enabled when the UART error interrupt is asserted
1 : Enable
DMA receive request outputs are disabled when the UART error interrupt is asserted
End of enumeration elements list.
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.