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I2C

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xFC byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR

ISR

TSR

SMPR

TOR

IMR

IER

IDR

GFCR

SR

AR

DR


CR

Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW MS NEA ACKEN HOLD SLVMON CLRFIFO DIV_A DIV_B

RW : Read/Write: Direction of transfer 0 - master transmitter, 1 - master receiver This bit is used in master mode only.
bits : 0 - 0 (1 bit)

MS : Master/Slave: Overall interface mode 0 - slave, 1 - master
bits : 1 - 2 (2 bit)

NEA : Normal/Extended Address:
bits : 2 - 4 (3 bit)

ACKEN : Acknowledge Enable: Enable transmission of ACK when master-receiver 0 – acknowledge disabled, NACK transmitted, 1 – acknowledge enabled, ACK transmitted This bit must always be set if FIFO is implemented.
bits : 3 - 6 (4 bit)

HOLD : Hold mode: Hold I2C sclk low until host services the data resources or clears this bit 1 - when no more data is available for transmit or no more data can be received, hold the sclk line low until serviced by the host. 0 - allow the transfer to terminate as soon as all the data has been transmitted or received. This bit has the same meaning in both master and slave modes.
bits : 4 - 8 (5 bit)

SLVMON : Slave Monitor mode: Slave monitor mode. 0 - normal operation, 1 - monitor mode
bits : 5 - 10 (6 bit)

CLRFIFO : Clear FIFO: initializes the FIFO to all zeros and clears the transfer size register
bits : 6 - 12 (7 bit)

DIV_A : Divisor A: Divisor for stage A clock divider. Divides the input pclk frequency by divisor_a + 1
bits : 8 - 21 (14 bit)

DIV_B : Divisor B: Divisor for stage B clock divider. Divides the output frequency from divisor_a by divisor_b + 1
bits : 14 - 29 (16 bit)


ISR

Interrupt Status Register
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMP DATA NACK TO SLV_RDY RX_OVF TX_OVF RX_UNF ARB_LOST

COMP : Transfer Complete
bits : 0 - 0 (1 bit)

DATA : More Data
bits : 1 - 2 (2 bit)

NACK : Transfer Not Acknowledged
bits : 2 - 4 (3 bit)

TO : Transfer Time Out
bits : 3 - 6 (4 bit)

SLV_RDY : Monitored Slave Ready
bits : 4 - 8 (5 bit)

RX_OVF : Receive Overflow
bits : 5 - 10 (6 bit)

TX_OVF : FIFO Transmit Overflow
bits : 6 - 12 (7 bit)

RX_UNF : FIFO Receive Underflow
bits : 7 - 14 (8 bit)

ARB_LOST : Arbitration Lost
bits : 9 - 18 (10 bit)


TSR

Transfer Size Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TSR TSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TS

TS : Transfer Size
bits : 0 - 3 (4 bit)


SMPR

Slave Monitor Pause Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMPR SMPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PI

PI : Pause Interval
bits : 0 - 3 (4 bit)


TOR

Time Out Register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TOR TOR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TO

TO : Time Out
bits : 0 - 7 (8 bit)


IMR

Interrupt Mask Register
address_offset : 0x20 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IMR IMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMP DATA NACK TO SLV_RDY RX_OVF TX_OVF RX_UNF ARB_LOST

COMP : Transfer Complete
bits : 0 - 0 (1 bit)

DATA : More Data
bits : 1 - 2 (2 bit)

NACK : Transfer Not Acknowledged
bits : 2 - 4 (3 bit)

TO : Transfer Time Out
bits : 3 - 6 (4 bit)

SLV_RDY : Monitored Slave Ready
bits : 4 - 8 (5 bit)

RX_OVF : Receive Overflow
bits : 5 - 10 (6 bit)

TX_OVF : FIFO Transmit Overflow
bits : 6 - 12 (7 bit)

RX_UNF : FIFO Receive Underflow
bits : 7 - 14 (8 bit)

ARB_LOST : Arbitration Lost
bits : 9 - 18 (10 bit)


IER

Interrupt Enable Register
address_offset : 0x24 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IER IER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMP DATA NACK TO SLV_RDY RX_OVF TX_OVF RX_UNF ARB_LOST

COMP : Transfer Complete
bits : 0 - 0 (1 bit)

DATA : More Data
bits : 1 - 2 (2 bit)

NACK : Transfer Not Acknowledged
bits : 2 - 4 (3 bit)

TO : Transfer Time Out
bits : 3 - 6 (4 bit)

SLV_RDY : Monitored Slave Ready
bits : 4 - 8 (5 bit)

RX_OVF : Receive Overflow
bits : 5 - 10 (6 bit)

TX_OVF : FIFO Transmit Overflow
bits : 6 - 12 (7 bit)

RX_UNF : FIFO Receive Underflow
bits : 7 - 14 (8 bit)

ARB_LOST : Arbitration Lost
bits : 9 - 18 (10 bit)


IDR

Interrupt Disable Register
address_offset : 0x28 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDR IDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMP DATA NACK TO SLV_RDY RX_OVF TX_OVF RX_UNF ARB_LOST

COMP : Transfer Complete
bits : 0 - 0 (1 bit)

DATA : More Data
bits : 1 - 2 (2 bit)

NACK : Transfer Not Acknowledged
bits : 2 - 4 (3 bit)

TO : Transfer Time Out
bits : 3 - 6 (4 bit)

SLV_RDY : Monitored Slave Ready
bits : 4 - 8 (5 bit)

RX_OVF : Receive Overflow
bits : 5 - 10 (6 bit)

TX_OVF : FIFO Transmit Overflow
bits : 6 - 12 (7 bit)

RX_UNF : FIFO Receive Underflow
bits : 7 - 14 (8 bit)

ARB_LOST : Arbitration Lost
bits : 9 - 18 (10 bit)


GFCR

Glitch Filter Control Register
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GFCR GFCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GF

GF : Glitch Filter depth
bits : 0 - 3 (4 bit)


SR

Status Register
address_offset : 0x4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRW RXDV TXDV RXOVF BA

RXRW : RX read/write flag: Indicates the mode of the transmission received from a master.
bits : 3 - 6 (4 bit)

RXDV : Receiver Data Valid: Indicates that there is valid, new data to be read from the interface.
bits : 5 - 10 (6 bit)

TXDV : Transmitter Data Valid: Indicates that there is still a byte of data to be transmitted by the interface.
bits : 6 - 12 (7 bit)

RXOVF : Receiver Overflow: This flag is set when the receiver receives a byte of data before the previous byte has been read by the host.
bits : 7 - 14 (8 bit)

BA : Bus Active: Indicates there is an ongoing transfer on the I2C bus. The I2C controller is not necessarily involved in it
bits : 8 - 16 (9 bit)


AR

Address Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AR AR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADD

ADD : I2C Address
bits : 0 - 9 (10 bit)


DR

Data Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DR DR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAT

DAT : I2C Data
bits : 0 - 7 (8 bit)



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