SYSCTRL

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

add a new register to this peripheral

SECDBGSTAT

FCLK_DIV

RESET_SYNDROME

RESET_MASK

SWRESET

GRETREG

INITSVTOR0

INITSVTOR1

CPUWAIT

NMI_ENABLE

WICCTRL

EWCTRL

SYSCLK_DIV

CLOCK_FORCE

PDCM_PD_SYS_SENSE

PDCM_PD_SRAM0_SENSE

PDCM_PD_SRAM1_SENSE

PDCM_PD_SRAM2_SENSE

PDCM_PD_SRAM3_SENSE

SECDBGSET

SECDBGCLR

SCSECCTRL


SECDBGSTAT

Secure Debug Configuration Status Register
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SECDBGSTAT SECDBGSTAT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FCLK_DIV

Fast Clock Divider Configuration Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FCLK_DIV FCLK_DIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESET_SYNDROME

Reset syndrome
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESET_SYNDROME RESET_SYNDROME read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESET_MASK

Reset MASK
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESET_MASK RESET_MASK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SWRESET

Software Reset
address_offset : 0x108 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SWRESET SWRESET write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GRETREG

General Purpose Retention Register
address_offset : 0x10C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GRETREG GRETREG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

INITSVTOR0

Initial Secure Reset Vector Register For CPU 0
address_offset : 0x110 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INITSVTOR0 INITSVTOR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

INITSVTOR1

Initial Secure Reset Vector Register For CPU 1
address_offset : 0x114 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INITSVTOR1 INITSVTOR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CPUWAIT

CPU Boot wait control after reset
address_offset : 0x118 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPUWAIT CPUWAIT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NMI_ENABLE

NMI Enable Register
address_offset : 0x11C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NMI_ENABLE NMI_ENABLE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

WICCTRL

CPU WIC Request and Acknowledgement
address_offset : 0x120 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WICCTRL WICCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EWCTRL

External Wakeup Control
address_offset : 0x124 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EWCTRL EWCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SYSCLK_DIV

System Clock Divider Configuration Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCLK_DIV SYSCLK_DIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CLOCK_FORCE

Clock Forces
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLOCK_FORCE CLOCK_FORCE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDCM_PD_SYS_SENSE

Power Control Dependency Matrix PD_SYS Power Domain Sensitivity
address_offset : 0x200 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDCM_PD_SYS_SENSE PDCM_PD_SYS_SENSE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDCM_PD_SRAM0_SENSE

Power Control Dependency Matrix PD_SRAM0 Power Domain Sensitivity
address_offset : 0x20C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDCM_PD_SRAM0_SENSE PDCM_PD_SRAM0_SENSE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDCM_PD_SRAM1_SENSE

Power Control Dependency Matrix PD_SRAM1 Power Domain Sensitivity
address_offset : 0x210 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDCM_PD_SRAM1_SENSE PDCM_PD_SRAM1_SENSE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDCM_PD_SRAM2_SENSE

Power Control Dependency Matrix PD_SRAM2 Power Domain Sensitivity
address_offset : 0x214 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDCM_PD_SRAM2_SENSE PDCM_PD_SRAM2_SENSE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDCM_PD_SRAM3_SENSE

Power Control Dependency Matrix PD_SRAM3 Power Domain Sensitivity
address_offset : 0x218 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDCM_PD_SRAM3_SENSE PDCM_PD_SRAM3_SENSE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SECDBGSET

Secure Debug Configuration Set Register
address_offset : 0x4 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SECDBGSET SECDBGSET write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SECDBGCLR

Secure Debug Configuration Clear Register
address_offset : 0x8 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SECDBGCLR SECDBGCLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SCSECCTRL

System Control Security Control Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCSECCTRL SCSECCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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