\n

SCC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CLK_CTRL_SEL

CLK_POSTDIV_QSPI

IOPAD_PS

IOPAD_SR

IOPAD_IS

PVT_CTRL

SRAM_RW_MARGINE

STATIC_CONF_SIG0

STATIC_CONF_SIG1

CLK_POSTDIV_RTC

REQ_SET

REQ_CLEAR

PCSM_CTRL_OVEERIDE

PD_CPU0_ISO_OVEERIDE

PD_CPU1_ISO_OVEERIDE

SYS_SRAM_RW_ASSIST0

SYS_SRAM_RW_ASSIST1

SYS_SRAM_RW_ASSIST4

SYS_SRAM_RW_ASSIST5

REQ_EDGE_SEL

REQ_ENABLE

MRAM_CTRL0

MRAM_CTRL1

MRAM_CTRL2

MRAM_CTRL3

MRAM_CTRL4

MRAM_DIN0

MRAM_DIN1

MRAM_DIN2

CLK_POSTDIV_TEST

MRAM_DOUT0

MRAM_DOUT1

MRAM_DOUT2

MRAM_STATUS

SELECTION_CONTROL_REG

CTRL_BYPASS_DIV

AZ_CTRL

CASTOR_OTP_CTRL

BBGEN_CTRL

SPARE_CTRL1

PLL_CTRL_PLL0_CLK

CLK_CTRL_ENABLE

CLK_STATUS

CLK_PLL_PREDIV_CTRL

RESET_CTRL

CHIP_ID

IO_IN_STATUS

DBG_CTRL

SRAM_CTRL

INTR_CTRL

CPU0_VTOR

CPU0_VTOR_1

CPU1_VTOR

CPU1_VTOR_1

IOMUX_MAIN_INSEL

IOMUX_MAIN_OUTSEL

IOMUX_MAIN_OENSEL

CLK_BBGEN_DIV_CLK

IOMUX_MAIN_DEFAULT_IN

IOMUX_ALTF1_INSEL

IOMUX_ALTF1_OUTSEL

IOMUX_ALTF1_OENSEL

IOMUX_ALTF1_DEFAULT_IN

IOMUX_ALTF2_INSEL

IOMUX_ALTF2_OUTSEL

IOMUX_ALTF2_OENSEL

IOMUX_ALTF2_DEFAULT_IN

IOMUX_ALTF3_INSEL

IOMUX_ALTF3_OUTSEL

IOMUX_ALTF3_OENSEL

IOMUX_ALTF3_DEFAULT_IN

IOPAD_DS0

IOPAD_DS1

IOPAD_PE


CLK_CTRL_SEL

Clock Control Select Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CTRL_SEL CLK_CTRL_SEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL_PREMUX_CLK SEL_DAPSWMUX_CLK SEL_MAINMUX_CLK SEL_REFMUX_CLK SEL_RM38KMUX_CLK SEL_SCCMUX_CLK SEL_RM38P4_PREMUX_CLK CTRL_SEL_TEST_MUX_CLK CTRL_PLL_MUX_CLK_SEL

SEL_PREMUX_CLK : Select PREMUX input: 0: 32K, 1: FASTCLK
bits : 0 - 0 (1 bit)

SEL_DAPSWMUX_CLK : Select DAPSWMUX input: 0: PRE_MUX_CLK, 1: JTAG TCK
bits : 1 - 2 (2 bit)

SEL_MAINMUX_CLK : Select MAINMUX input: 0: PLL0_CLK, 1: PRE_MUX_CLK
bits : 2 - 4 (3 bit)

SEL_REFMUX_CLK : Select REFMUX input: 0: PRE_MUX_CLK, 1: PRE_PLL_CLK
bits : 3 - 6 (4 bit)

SEL_RM38KMUX_CLK : Select RM38KMUX input: 0: REF_MUX_CLK, 1: RM38K (not used)
bits : 4 - 8 (5 bit)

SEL_SCCMUX_CLK : Select SCCMUX input: 0: SCCCLK, 1: PRE_MUX_CLK
bits : 5 - 10 (6 bit)

SEL_RM38P4_PREMUX_CLK : Select RM38KPREMUX input: 0: SYSSYSSUGCLK, 1: NRM138P4 (not used)
bits : 6 - 12 (7 bit)

CTRL_SEL_TEST_MUX_CLK : Select TESTMUX input
bits : 7 - 18 (12 bit)

CTRL_PLL_MUX_CLK_SEL : PLL MUX select: 0: PLL0, 1: Not used
bits : 12 - 24 (13 bit)


CLK_POSTDIV_QSPI

QSPI Divider
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_POSTDIV_QSPI CLK_POSTDIV_QSPI read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 postdiv_ctrl_qspi_div_clk

postdiv_ctrl_qspi_div_clk : qspi_div_clk value
bits : 0 - 7 (8 bit)


IOPAD_PS

IO Pad Pull Select Register
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOPAD_PS IOPAD_PS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IOPAD_SR

IO Pad Slew Rate Register
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOPAD_SR IOPAD_SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IOPAD_IS

IO Pad Input Mode Select Register
address_offset : 0x110 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOPAD_IS IOPAD_IS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PVT_CTRL

PVT Control Register
address_offset : 0x118 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PVT_CTRL PVT_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSTSENNUM TSTGRPSEL

TSTSENNUM : Test SEN number
bits : 0 - 4 (5 bit)

TSTGRPSEL : Test group select
bits : 5 - 10 (6 bit)


SRAM_RW_MARGINE

SRAM Read/Write Margin Control Register
address_offset : 0x134 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRAM_RW_MARGINE SRAM_RW_MARGINE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RM0 WM0 RM1 WM1 RM2 WM2 RM3 WM3

RM0 : Read margin control for code srams: u_sram_64k_0 .. u_sram_64k_7
bits : 0 - 2 (3 bit)

WM0 : Write margin control for code srams: u_sram_64k_0 .. u_sram_64k_7
bits : 4 - 9 (6 bit)

RM1 : Read margin control for code srams: u_sram_64k_8 .. u_sram_64k_15
bits : 8 - 18 (11 bit)

WM1 : Write margin control for code srams: u_sram_64k_8 .. u_sram_64k_15
bits : 12 - 25 (14 bit)

RM2 : Read margin control for code srams: u_sram_64k_16 .. u_sram_64k_23
bits : 16 - 34 (19 bit)

WM2 : Write margin control for code srams: u_sram_64k_16 .. u_sram_64k_23
bits : 20 - 41 (22 bit)

RM3 : Read margin control for code srams: u_sram_64k_24 .. u_sram_64k_31
bits : 24 - 50 (27 bit)

WM3 : Write margin control for code srams: u_sram_64k_24 .. u_sram_64k_31
bits : 28 - 57 (30 bit)


STATIC_CONF_SIG0


address_offset : 0x138 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATIC_CONF_SIG0 STATIC_CONF_SIG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTMCHCISBYPASS CTMCHCIHSBYPASS DBGENSELDIS NIDENSELDIS SPIDENSELDIS SPNIDENSELDIS

CTMCHCISBYPASS : Cross Trigger Channel Interface Configuration
bits : 0 - 0 (1 bit)

CTMCHCIHSBYPASS : Cross Trigger Channel Interface Configuarion
bits : 1 - 5 (5 bit)

DBGENSELDIS : DBGEN Selector Disable
bits : 5 - 10 (6 bit)

NIDENSELDIS : NIDEN Selector Disable
bits : 6 - 12 (7 bit)

SPIDENSELDIS : SPIDEN Selector Disable
bits : 7 - 14 (8 bit)

SPNIDENSELDIS : SPNIDEN Selector Disable
bits : 8 - 16 (9 bit)


STATIC_CONF_SIG1


address_offset : 0x13C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATIC_CONF_SIG1 STATIC_CONF_SIG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TISBYPASSIN TISBYPASSACK TIHSBYPASS TINIDENSEL TODBGENSEL

TISBYPASSIN : Cross Trigger Interface synchronous bypass on CTITRIGIN
bits : 0 - 7 (8 bit)

TISBYPASSACK : Cross Trigger Interface synchronous bypass on CTITRIGOUTACK
bits : 8 - 19 (12 bit)

TIHSBYPASS : Cross Trigger interface handshake bypass on CTITRIGOUT
bits : 12 - 27 (16 bit)

TINIDENSEL : NIDEN mask on CTITRIGINT
bits : 16 - 39 (24 bit)

TODBGENSEL : DBGEN mask on CTITRIGOUT
bits : 24 - 51 (28 bit)


CLK_POSTDIV_RTC

RTC Divider
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_POSTDIV_RTC CLK_POSTDIV_RTC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 postdiv_ctrl_rtc_div_clk

postdiv_ctrl_rtc_div_clk : rtc_div_clk value
bits : 0 - 31 (32 bit)


REQ_SET

Clock and Power Request Set Register
address_offset : 0x140 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REQ_SET REQ_SET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 clk_req_set pwr_req_set pwr_req_set_en

clk_req_set : Set SYSMAINCLKREQUEST
bits : 0 - 0 (1 bit)

pwr_req_set : Set SYSPOWERREQUEST
bits : 1 - 5 (5 bit)

pwr_req_set_en : External event enable
bits : 8 - 19 (12 bit)


REQ_CLEAR

Clock and Power Request Clear Register
address_offset : 0x144 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REQ_CLEAR REQ_CLEAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 clk_req_clear pwr_req_clear

clk_req_clear : Clock request clear
bits : 0 - 0 (1 bit)

pwr_req_clear : Power request clear
bits : 1 - 5 (5 bit)


PCSM_CTRL_OVEERIDE

PCSM Control Override Register
address_offset : 0x148 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCSM_CTRL_OVEERIDE PCSM_CTRL_OVEERIDE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSSYSCLKQACTIVE SYSFCLKQACTIVE CRYPTOSYSCLKQACTIVE BCRYPTOSPIKCLKQACTIVE CRYPTOPWRQACTIVE SYSPWRQACTIVE DEBUGPIKCLKQACTIVE DBGPWRQACTIVE DEBUGPIKCLKQACTIVE_en DBGPWRQACTIVE_en

SYSSYSCLKQACTIVE : Q-Channels QACTIVE Override
bits : 0 - 0 (1 bit)

SYSFCLKQACTIVE : Q-Channels QACTIVE Override
bits : 1 - 2 (2 bit)

CRYPTOSYSCLKQACTIVE : Q-Channels QACTIVE Override
bits : 2 - 4 (3 bit)

BCRYPTOSPIKCLKQACTIVE : Q-Channels QACTIVE Override
bits : 3 - 6 (4 bit)

CRYPTOPWRQACTIVE : Q-Channels QACTIVE Override
bits : 4 - 8 (5 bit)

SYSPWRQACTIVE : Q-Channels QACTIVE Override
bits : 5 - 10 (6 bit)

DEBUGPIKCLKQACTIVE : Q-Channels QACTIVE Override
bits : 6 - 12 (7 bit)

DBGPWRQACTIVE : Q-Channels QACTIVE Override
bits : 7 - 14 (8 bit)

DEBUGPIKCLKQACTIVE_en : Q-Channels QACTIVE Override
bits : 8 - 16 (9 bit)

DBGPWRQACTIVE_en : Q-Channels QACTIVE Override
bits : 9 - 18 (10 bit)


PD_CPU0_ISO_OVEERIDE


address_offset : 0x14C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD_CPU0_ISO_OVEERIDE PD_CPU0_ISO_OVEERIDE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHSEC_FREQ_SEL CHSEC_BYPASS CHSEC_DISCHARGE_CNTL CHSEC_SE_CNTL CHSEC_ISO_ENB CHSEC_MISC

CHSEC_FREQ_SEL : Secure Frame Frequency select
bits : 0 - 1 (2 bit)

CHSEC_BYPASS : Secure Frame Bypass
bits : 2 - 4 (3 bit)

CHSEC_DISCHARGE_CNTL : Secure Frame discharge control
bits : 3 - 6 (4 bit)

CHSEC_SE_CNTL : Secure Frame Scan Enable control
bits : 4 - 8 (5 bit)

CHSEC_ISO_ENB : Secure Frame Isolation Enable
bits : 5 - 10 (6 bit)

CHSEC_MISC : Secure Frame Control
bits : 8 - 23 (16 bit)


PD_CPU1_ISO_OVEERIDE

CPU1 Isolation Override Register
address_offset : 0x150 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD_CPU1_ISO_OVEERIDE PD_CPU1_ISO_OVEERIDE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SYS_SRAM_RW_ASSIST0

CPU0 SRAM Read/Write Margin Control Register
address_offset : 0x154 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_SRAM_RW_ASSIST0 SYS_SRAM_RW_ASSIST0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RM0 WM0 RM1 WM1

RM0 : Castor cpu0 tag_sram_0 read margin
bits : 0 - 2 (3 bit)

WM0 : Castor cpu0 tag_sram_0 write margin
bits : 4 - 9 (6 bit)

RM1 : Castor cpu0 tag_sram_1 read margin
bits : 16 - 34 (19 bit)

WM1 : Castor cpu0 tag_sram_1 write margin
bits : 20 - 41 (22 bit)


SYS_SRAM_RW_ASSIST1

CPU1 SRAM Read/Write Margin Control Register
address_offset : 0x158 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_SRAM_RW_ASSIST1 SYS_SRAM_RW_ASSIST1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RM0 WM0 RM1 WM1

RM0 : Castor cpu1 tag_sram_0 read margin
bits : 0 - 2 (3 bit)

WM0 : Castor cpu1 tag_sram_0 write margin
bits : 4 - 9 (6 bit)

RM1 : Castor cpu1 tag_sram_1 read margin
bits : 16 - 34 (19 bit)

WM1 : Castor cpu1 tag_sram_1 write margin
bits : 20 - 41 (22 bit)


SYS_SRAM_RW_ASSIST4

Core 0/1 SRAM Read/Write Margin Control Register
address_offset : 0x164 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_SRAM_RW_ASSIST4 SYS_SRAM_RW_ASSIST4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RM0 WM0 RM1 WM1 RM2 WM2 RM3 WM3

RM0 : Castor core_0 sram_0 read margin
bits : 0 - 2 (3 bit)

WM0 : Castor core_0 sram_0 write margin
bits : 4 - 9 (6 bit)

RM1 : Castor core_0 sram_1 read margin
bits : 8 - 18 (11 bit)

WM1 : Castor core_0 sram_1 write margin
bits : 12 - 25 (14 bit)

RM2 : Castor core_1 sram_0 read margin
bits : 16 - 34 (19 bit)

WM2 : Castor core_1 sram_0 write margin
bits : 20 - 41 (22 bit)

RM3 : Castor core_1 sram_1 read margin
bits : 24 - 50 (27 bit)

WM3 : Castor core_1 sram_1 write margin
bits : 28 - 57 (30 bit)


SYS_SRAM_RW_ASSIST5

Core 2/3 SRAM Read/Write Margin Control Register
address_offset : 0x168 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_SRAM_RW_ASSIST5 SYS_SRAM_RW_ASSIST5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RM0 WM0 RM1 WM1 RM2 WM2 RM3 WM3

RM0 : Castor core_2 sram_0 read margin
bits : 0 - 2 (3 bit)

WM0 : Castor core_2 sram_0 write margin
bits : 4 - 9 (6 bit)

RM1 : Castor core_2 sram_1 read margin
bits : 8 - 18 (11 bit)

WM1 : Castor core_2 sram_1 write margin
bits : 12 - 25 (14 bit)

RM2 : Castor core_3 sram_0 read margin
bits : 16 - 34 (19 bit)

WM2 : Castor core_3 sram_0 write margin
bits : 20 - 41 (22 bit)

RM3 : Castor core_3 sram_1 read margin
bits : 24 - 50 (27 bit)

WM3 : Castor core_3 sram_1 write margin
bits : 28 - 57 (30 bit)


REQ_EDGE_SEL

Clock and Power Request Edge Select Register
address_offset : 0x184 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REQ_EDGE_SEL REQ_EDGE_SEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

REQ_ENABLE

Clock and Power Request Enable Register
address_offset : 0x188 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REQ_ENABLE REQ_ENABLE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MRAM_CTRL0

eMRAM Control 0 Register
address_offset : 0x198 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MRAM_CTRL0 MRAM_CTRL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mram_clk_en proc_spec_clk_en autostop_en mram_inv_clk_sel fast_read_en mram_dout_sel PG_VDD_0 PG_VDD18_0 PG_VDD_1 PG_VDD18_1 write_csn_clks csn_high_clks read_csn_clks mram_otp_clk_en mram_clk_sync_bypass mram_da_en

mram_clk_en : eMRAM clock enable
bits : 0 - 0 (1 bit)

proc_spec_clk_en : eMRAM controller clock enable
bits : 1 - 2 (2 bit)

autostop_en : Auto stop enable
bits : 2 - 4 (3 bit)

mram_inv_clk_sel : eMRAM clock invert select
bits : 3 - 6 (4 bit)

fast_read_en : Fast read enable
bits : 4 - 8 (5 bit)

mram_dout_sel : eMRAM data out select
bits : 6 - 11 (6 bit)

PG_VDD_0 : eMRAM0 PG VDD
bits : 8 - 16 (9 bit)

PG_VDD18_0 : eMRAM0 PG VDD18
bits : 9 - 18 (10 bit)

PG_VDD_1 : eMRAM1 PG VDD
bits : 10 - 20 (11 bit)

PG_VDD18_1 : eMRAM1 PG VDD18
bits : 11 - 22 (12 bit)

write_csn_clks : Number of clock cycles for single write operation
bits : 12 - 27 (16 bit)

csn_high_clks : Number of clock cycles to wait when CSN is high before going to new access
bits : 16 - 35 (20 bit)

read_csn_clks : Number of clocks cycles for single read operation
bits : 20 - 43 (24 bit)

mram_otp_clk_en : eMRAM OTP clock enable
bits : 29 - 58 (30 bit)

mram_clk_sync_bypass : eMRAM clock sync bypass
bits : 30 - 60 (31 bit)

mram_da_en : eMRAM direct access enable
bits : 31 - 62 (32 bit)


MRAM_CTRL1

eMRAM Control 1 Register
address_offset : 0x19C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MRAM_CTRL1 MRAM_CTRL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mram_da_addr mram_da_ctrl

mram_da_addr : eMRAM direct access address
bits : 0 - 23 (24 bit)

mram_da_ctrl : eMRAM direct access controls
bits : 24 - 55 (32 bit)


MRAM_CTRL2

eMRAM Control 2 Register
address_offset : 0x1A0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MRAM_CTRL2 MRAM_CTRL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 prescale mram_clk_div time_to_stop

prescale : eMRAM clock frequency value
bits : 0 - 7 (8 bit)

mram_clk_div : eMRAM clock divider
bits : 8 - 23 (16 bit)

time_to_stop : Number of useconds to wait in inactive mode before going to STOP mode if auto_stop is enabled
bits : 16 - 47 (32 bit)


MRAM_CTRL3

eMRAM Control 3 Register
address_offset : 0x1A4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MRAM_CTRL3 MRAM_CTRL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEST_MODE WRSTN STOP_TM RESETB_TM PG_VDD_TM PG_VDD18_TM M_SEL DA0 DA1 SCAN_MODE TST_SCANENABLE PDN_SCAN WRCK ShiftWR SelectWIR CaptureWR RBACT1 UpdateWR WSI TST_SCANIN mram_stop mram_resetb mram_load_start mram_load_rstn

TEST_MODE : Access by SCC at functional mode
bits : 0 - 2 (3 bit)

WRSTN : Access by SCC at functional mode
bits : 3 - 6 (4 bit)

STOP_TM : Access by SCC at functional mode
bits : 4 - 8 (5 bit)

RESETB_TM : Access by SCC at functional mode
bits : 5 - 10 (6 bit)

PG_VDD_TM : Access by SCC at functional mode
bits : 6 - 12 (7 bit)

PG_VDD18_TM : Access by SCC at functional mode
bits : 7 - 14 (8 bit)

M_SEL : Access by SCC at functional mode
bits : 8 - 16 (9 bit)

DA0 : Access by SCC at functional mode
bits : 9 - 18 (10 bit)

DA1 : Access by SCC at functional mode
bits : 10 - 20 (11 bit)

SCAN_MODE : Access by SCC at functional mode
bits : 11 - 22 (12 bit)

TST_SCANENABLE : Access by SCC at functional mode
bits : 12 - 24 (13 bit)

PDN_SCAN : Access by SCC at functional mode
bits : 13 - 26 (14 bit)

WRCK : Access by SCC at functional mode
bits : 16 - 32 (17 bit)

ShiftWR : Access by SCC at functional mode
bits : 17 - 34 (18 bit)

SelectWIR : Access by SCC at functional mode
bits : 18 - 36 (19 bit)

CaptureWR : Access by SCC at functional mode
bits : 19 - 38 (20 bit)

RBACT1 : Access by SCC at functional mode
bits : 20 - 40 (21 bit)

UpdateWR : Access by SCC at functional mode
bits : 21 - 42 (22 bit)

WSI : Access by SCC at functional mode
bits : 22 - 44 (23 bit)

TST_SCANIN : Access by SCC at functional mode
bits : 23 - 50 (28 bit)

mram_stop : Access by SCC at functional mode
bits : 28 - 56 (29 bit)

mram_resetb : Access by SCC at functional mode
bits : 29 - 58 (30 bit)

mram_load_start : Access by SCC at functional mode
bits : 30 - 60 (31 bit)

mram_load_rstn : Access by SCC at functional mode
bits : 31 - 62 (32 bit)


MRAM_CTRL4

eMRAM Control 4 Register
address_offset : 0x1A8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MRAM_CTRL4 MRAM_CTRL4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CK_TM CSN_TM WEN_TM DIN_DA_SPLIT DQ_SEL OTP_LOAD_RSTn_TM OTP_LOAD_START_TM Capture_OTP_LOAD_TM REG_CLK REG_RESET XA_CNT XA_CNT_SEL XA_ShiftorCapture XA_SI TCK TDI TMS TRST

CK_TM : Access by SCC at functional mode
bits : 0 - 0 (1 bit)

CSN_TM : Access by SCC at functional mode
bits : 1 - 2 (2 bit)

WEN_TM : Access by SCC at functional mode
bits : 2 - 4 (3 bit)

DIN_DA_SPLIT : Access by SCC at functional mode
bits : 4 - 15 (12 bit)

DQ_SEL : Access by SCC at functional mode
bits : 12 - 27 (16 bit)

OTP_LOAD_RSTn_TM : Access by SCC at functional mode
bits : 16 - 32 (17 bit)

OTP_LOAD_START_TM : Access by SCC at functional mode
bits : 17 - 34 (18 bit)

Capture_OTP_LOAD_TM : Access by SCC at functional mode
bits : 18 - 36 (19 bit)

REG_CLK : Access by SCC at functional mode
bits : 19 - 38 (20 bit)

REG_RESET : Access by SCC at functional mode
bits : 20 - 40 (21 bit)

XA_CNT : Access by SCC at functional mode
bits : 21 - 42 (22 bit)

XA_CNT_SEL : Access by SCC at functional mode
bits : 22 - 44 (23 bit)

XA_ShiftorCapture : Access by SCC at functional mode
bits : 23 - 46 (24 bit)

XA_SI : Access by SCC at functional mode
bits : 24 - 48 (25 bit)

TCK : Access by SCC at functional mode
bits : 25 - 50 (26 bit)

TDI : Access by SCC at functional mode
bits : 26 - 52 (27 bit)

TMS : Access by SCC at functional mode
bits : 27 - 54 (28 bit)

TRST : Access by SCC at functional mode
bits : 28 - 56 (29 bit)


MRAM_DIN0

eMRAM input data mram_din[31:0]
address_offset : 0x1B0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MRAM_DIN0 MRAM_DIN0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MRAM_DIN1

eMRAM input data mram_din[63:32]
address_offset : 0x1B4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MRAM_DIN1 MRAM_DIN1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MRAM_DIN2

eMRAM input data mram_din[77:64]
address_offset : 0x1B8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MRAM_DIN2 MRAM_DIN2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CLK_POSTDIV_TEST

Test Divider
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_POSTDIV_TEST CLK_POSTDIV_TEST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 postdiv_ctrl_test_div_clk

postdiv_ctrl_test_div_clk : test_div_clk value
bits : 0 - 7 (8 bit)


MRAM_DOUT0

eMRAM output data mram_dout[31:0]
address_offset : 0x1C0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MRAM_DOUT0 MRAM_DOUT0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MRAM_DOUT1

eMRAM output data mram_dout[63:32]
address_offset : 0x1C4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MRAM_DOUT1 MRAM_DOUT1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MRAM_DOUT2

eMRAM output data mram_dout[77:64]
address_offset : 0x1C8 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MRAM_DOUT2 MRAM_DOUT2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MRAM_STATUS

eMRAM Status Register
address_offset : 0x1CC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MRAM_STATUS MRAM_STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 fsm_state mram_test_mode

fsm_state : eMRAM controller FSM state
bits : 0 - 4 (5 bit)

mram_test_mode : eMRAM test mode
bits : 5 - 12 (8 bit)


SELECTION_CONTROL_REG

Selection Control Register
address_offset : 0x1E0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SELECTION_CONTROL_REG SELECTION_CONTROL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Clock_phase_shifter_select Clock_phase_shifter_bypass

Clock_phase_shifter_select : Clock phase shifter select
bits : 1 - 1 (1 bit)

Clock_phase_shifter_bypass : Clock phase shifter bypass
bits : 2 - 4 (3 bit)


CTRL_BYPASS_DIV

Bypass Divider Control Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL_BYPASS_DIV CTRL_BYPASS_DIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ctrl_bypass_div_pll_prediv_clk ctrl_bypass_div_qspi_div_clk ctrl_bypass_div_rtc_div_clk ctrl_bypass_div_test_div_clk

ctrl_bypass_div_pll_prediv_clk : pll_prediv_clk bypass value
bits : 0 - 0 (1 bit)

ctrl_bypass_div_qspi_div_clk : qspi_div_clk bypass value
bits : 3 - 6 (4 bit)

ctrl_bypass_div_rtc_div_clk : rtc_div_clk bypass value
bits : 4 - 8 (5 bit)

ctrl_bypass_div_test_div_clk : test_div_clk bypass value
bits : 6 - 12 (7 bit)


AZ_CTRL

AZ Control Register
address_offset : 0x200 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AZ_CTRL AZ_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCC_nPORESETAON_nPORESET_SEL

SCC_nPORESETAON_nPORESET_SEL : Memory subsystem reset select: 1: nPORESETAON 0: NPORESET
bits : 9 - 18 (10 bit)


CASTOR_OTP_CTRL

OTP Control Register
address_offset : 0x204 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CASTOR_OTP_CTRL CASTOR_OTP_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 scc_addr scc_din scc_web scc_readen scc_otp_ctrl pad_sel scc_sel

scc_addr : otp addr from scc
bits : 0 - 15 (16 bit)

scc_din : din from scc
bits : 16 - 32 (17 bit)

scc_web : web from scc
bits : 17 - 34 (18 bit)

scc_readen : readen from scc
bits : 18 - 36 (19 bit)

scc_otp_ctrl : scc otp control
bits : 20 - 49 (30 bit)

pad_sel : OTP control selection
bits : 30 - 60 (31 bit)

scc_sel : OTP control selection
bits : 31 - 62 (32 bit)


BBGEN_CTRL

Body Bias Enable Control Register
address_offset : 0x220 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BBGEN_CTRL BBGEN_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SPARE_CTRL1

Spare 1 Control Register
address_offset : 0x224 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPARE_CTRL1 SPARE_CTRL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PLL_CTRL_PLL0_CLK

PLL0 Control Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLL_CTRL_PLL0_CLK PLL_CTRL_PLL0_CLK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Pll0_M Pll0_S Pll0_EXTAFC Pll0_AFC_ENB Pll0_BYPASS Pll1_RESETB Pll0_RESETB

Pll0_M : Control pins to change the target frequency of internal oscillator
bits : 0 - 11 (12 bit)

Pll0_S : Division value of the 3-bit programmable scaler
bits : 12 - 26 (15 bit)

Pll0_EXTAFC : Monitoring pin
bits : 16 - 36 (21 bit)

Pll0_AFC_ENB : Monitoring pin
bits : 28 - 56 (29 bit)

Pll0_BYPASS : bypass mode
bits : 29 - 58 (30 bit)

Pll1_RESETB : Power down
bits : 30 - 60 (31 bit)

Pll0_RESETB : Power down
bits : 31 - 62 (32 bit)


CLK_CTRL_ENABLE

Clock Control Enable Register
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CTRL_ENABLE CLK_CTRL_ENABLE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ctrl_enable_clk1hz ctrl_enable_dapswclk ctrl_enable_gpiohclk ctrl_enable_i2sclk0 ctrl_enable_i2sclk1 ctrl_enable_i2sclk2 ctrl_enable_mainclk ctrl_enable_qspiphyclk ctrl_enable_refclk ctrl_enable_rm38kclk ctrl_enable_sccclk ctrl_enable_taptck ctrl_enable_testclk

ctrl_enable_clk1hz : rtc_div_clk enable
bits : 0 - 0 (1 bit)

ctrl_enable_dapswclk : dapsw_mux_clk enable
bits : 1 - 2 (2 bit)

ctrl_enable_gpiohclk : I_SYSSYSUGCLK enable
bits : 2 - 4 (3 bit)

ctrl_enable_i2sclk0 : I_SYSSYSUGCLK enable
bits : 3 - 6 (4 bit)

ctrl_enable_i2sclk1 : I_SYSSYSUGCLK enable
bits : 4 - 8 (5 bit)

ctrl_enable_i2sclk2 : I_SYSSYSUGCLK enable
bits : 5 - 10 (6 bit)

ctrl_enable_mainclk : main_mux_clk enable
bits : 8 - 16 (9 bit)

ctrl_enable_qspiphyclk : qspi_div_clk enable
bits : 9 - 18 (10 bit)

ctrl_enable_refclk : ref_mux_clk enable
bits : 10 - 20 (11 bit)

ctrl_enable_rm38kclk : rm38k_mux_clk enable
bits : 11 - 22 (12 bit)

ctrl_enable_sccclk : scc_mux_clk enable
bits : 12 - 24 (13 bit)

ctrl_enable_taptck : tck_mux_clk enable
bits : 14 - 28 (15 bit)

ctrl_enable_testclk : test_div_clk enable
bits : 15 - 30 (16 bit)


CLK_STATUS

Clock Status Register
address_offset : 0x34 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CLK_STATUS CLK_STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 status_out_clk_mainclk_ready status_lock_signal_pll0_clk

status_out_clk_mainclk_ready : Clock ready (active)
bits : 0 - 0 (1 bit)

status_lock_signal_pll0_clk : PLL Lock Status
bits : 1 - 2 (2 bit)


CLK_PLL_PREDIV_CTRL

PLL Predivider Control Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_PLL_PREDIV_CTRL CLK_PLL_PREDIV_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PREDIV_CTRL

PREDIV_CTRL : PLL0 pre-divider value: Divison value = PREDIV_CTRL+1
bits : 0 - 9 (10 bit)


RESET_CTRL

Reset Control Register
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESET_CTRL RESET_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPTIMER_RESET I2C0_RESET I2C1_RESET I2S_RESET SPI_RESET QSPI_RESET UART0_RESET UART1_RESET GPIO_RESET PVT_RESET PWM0_RESET PWM1_RESET PWM2_RESET RTC_RESET CASTOR_NSRST_PSI_Sel CASTOR_NSRST_Sel CASTOR_NSRST

GPTIMER_RESET : Reset Active low
bits : 1 - 2 (2 bit)

I2C0_RESET : Reset Active low
bits : 2 - 4 (3 bit)

I2C1_RESET : Reset Active low
bits : 3 - 6 (4 bit)

I2S_RESET : Reset Active low
bits : 4 - 8 (5 bit)

SPI_RESET : Reset Active low
bits : 5 - 10 (6 bit)

QSPI_RESET : Reset Active low
bits : 6 - 12 (7 bit)

UART0_RESET : Reset Active low
bits : 7 - 14 (8 bit)

UART1_RESET : Reset Active low
bits : 8 - 16 (9 bit)

GPIO_RESET : Reset Active low
bits : 9 - 18 (10 bit)

PVT_RESET : Reset Active low
bits : 10 - 20 (11 bit)

PWM0_RESET : Reset Active low
bits : 11 - 22 (12 bit)

PWM1_RESET : Reset Active low
bits : 12 - 24 (13 bit)

PWM2_RESET : Reset Active low
bits : 13 - 26 (14 bit)

RTC_RESET : Reset Active low
bits : 14 - 28 (15 bit)

CASTOR_NSRST_PSI_Sel : Reset Active low
bits : 15 - 30 (16 bit)

CASTOR_NSRST_Sel : Reset Active low
bits : 16 - 32 (17 bit)

CASTOR_NSRST : Reset Active low
bits : 17 - 34 (18 bit)


CHIP_ID

Chip ID Register
address_offset : 0x400 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHIP_ID CHIP_ID read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IO_IN_STATUS

GP IO Pads Input Status Register
address_offset : 0x404 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IO_IN_STATUS IO_IN_STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DBG_CTRL

Debug Control Register
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBG_CTRL DBG_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBGENIN NIDENIN SPIDENIN SPNIDENIN TODBGENSEL dbg_dcu_force

DBGENIN : Castor DBGENIN
bits : 0 - 0 (1 bit)

NIDENIN : Castor NIDENIN
bits : 1 - 2 (2 bit)

SPIDENIN : Castor SPIDENIN
bits : 2 - 4 (3 bit)

SPNIDENIN : Castor SPNIDENIN
bits : 3 - 6 (4 bit)

TODBGENSEL : Debug expansion TODBGENSEL
bits : 8 - 15 (8 bit)

dbg_dcu_force : Castor DBG ports control 0: use Crypto DCU 1: Use SCC signals (force)
bits : 31 - 62 (32 bit)


SRAM_CTRL

SRAM Control Register
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRAM_CTRL SRAM_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 code_sram0_pgen code_sram1_pgen code_sram2_pgen code_sram3_pgen code_sram4_pgen code_sram5_pgen code_sram6_pgen code_sram7_pgen code_sram8_pgen code_sram9_pgen code_sram10_pgen code_sram11_pgen code_sram12_pgen code_sram13_pgen code_sram14_pgen code_sram15_pgen code_sram16_pgen code_sram17_pgen code_sram18_pgen code_sram19_pgen code_sram20_pgen code_sram21_pgen code_sram22_pgen code_sram23_pgen code_sram24_pgen code_sram25_pgen code_sram26_pgen code_sram27_pgen code_sram28_pgen code_sram29_pgen code_sram30_pgen code_sram31_pgen

code_sram0_pgen : 1st 64KB Code SRAM cell power gate enable
bits : 0 - 0 (1 bit)

code_sram1_pgen : 2nd 64KB Code SRAM cell power gate enable
bits : 1 - 2 (2 bit)

code_sram2_pgen : 3rd 64KB Code SRAM cell power gate enable
bits : 2 - 4 (3 bit)

code_sram3_pgen : 4th 64KB Code SRAM cell power gate enable
bits : 3 - 6 (4 bit)

code_sram4_pgen : 5th 64KB Code SRAM cell power gate enable
bits : 4 - 8 (5 bit)

code_sram5_pgen : 6th 64KB Code SRAM cell power gate enable
bits : 5 - 10 (6 bit)

code_sram6_pgen : 7th 64KB Code SRAM cell power gate enable
bits : 6 - 12 (7 bit)

code_sram7_pgen : 8th 64KB Code SRAM cell power gate enable
bits : 7 - 14 (8 bit)

code_sram8_pgen : 9th 64KB Code SRAM cell power gate enable
bits : 8 - 16 (9 bit)

code_sram9_pgen : 10th 64KB Code SRAM cell power gate enable
bits : 9 - 18 (10 bit)

code_sram10_pgen : 11st 64KB Code SRAM cell power gate enable
bits : 10 - 20 (11 bit)

code_sram11_pgen : 12th 64KB Code SRAM cell power gate enable
bits : 11 - 22 (12 bit)

code_sram12_pgen : 13th 64KB Code SRAM cell power gate enable
bits : 12 - 24 (13 bit)

code_sram13_pgen : 14th 64KB Code SRAM cell power gate enable
bits : 13 - 26 (14 bit)

code_sram14_pgen : 15th 64KB Code SRAM cell power gate enable
bits : 14 - 28 (15 bit)

code_sram15_pgen : 16th 64KB Code SRAM cell power gate enable
bits : 15 - 30 (16 bit)

code_sram16_pgen : 17th 64KB Code SRAM cell power gate enable
bits : 16 - 32 (17 bit)

code_sram17_pgen : 18th 64KB Code SRAM cell power gate enable
bits : 17 - 34 (18 bit)

code_sram18_pgen : 19th 64KB Code SRAM cell power gate enable
bits : 18 - 36 (19 bit)

code_sram19_pgen : 20th 64KB Code SRAM cell power gate enable
bits : 19 - 38 (20 bit)

code_sram20_pgen : 21st 64KB Code SRAM cell power gate enable
bits : 20 - 40 (21 bit)

code_sram21_pgen : 22th 64KB Code SRAM cell power gate enable
bits : 21 - 42 (22 bit)

code_sram22_pgen : 23th 64KB Code SRAM cell power gate enable
bits : 22 - 44 (23 bit)

code_sram23_pgen : 24th 64KB Code SRAM cell power gate enable
bits : 23 - 46 (24 bit)

code_sram24_pgen : 25th 64KB Code SRAM cell power gate enable
bits : 24 - 48 (25 bit)

code_sram25_pgen : 26th 64KB Code SRAM cell power gate enable
bits : 25 - 50 (26 bit)

code_sram26_pgen : 27th 64KB Code SRAM cell power gate enable
bits : 26 - 52 (27 bit)

code_sram27_pgen : 28th 64KB Code SRAM cell power gate enable
bits : 27 - 54 (28 bit)

code_sram28_pgen : 29th 64KB Code SRAM cell power gate enable
bits : 28 - 56 (29 bit)

code_sram29_pgen : 30th 64KB Code SRAM cell power gate enable
bits : 29 - 58 (30 bit)

code_sram30_pgen : 31st 64KB Code SRAM cell power gate enable
bits : 30 - 60 (31 bit)

code_sram31_pgen : 32th 64KB Code SRAM cell power gate enable
bits : 31 - 62 (32 bit)


INTR_CTRL

MPC Interrupt Control Register
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTR_CTRL INTR_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sram_mpc_cfg_init_value qspi_mpc_cfg_init_value mram_mpc_cfg_init_value

sram_mpc_cfg_init_value : sram mpc cfg init value
bits : 0 - 0 (1 bit)

qspi_mpc_cfg_init_value : qspi mpc cfg init value
bits : 1 - 2 (2 bit)

mram_mpc_cfg_init_value : mram mpc cfg init value
bits : 2 - 4 (3 bit)


CPU0_VTOR

CPU 0 VTOR Register
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPU0_VTOR CPU0_VTOR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CPU0_VTOR_1

CPU 0 VTOR 1 Register
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPU0_VTOR_1 CPU0_VTOR_1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CPU1_VTOR

CPU 1 VTROR Register
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPU1_VTOR CPU1_VTOR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CPU1_VTOR_1

CPU 1 VTOR 1 Register
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPU1_VTOR_1 CPU1_VTOR_1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IOMUX_MAIN_INSEL

IOMux Main Function Input Data Select Register
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOMUX_MAIN_INSEL IOMUX_MAIN_INSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IOMUX_MAIN_OUTSEL

IOMux Main Function Output Data Select Register
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOMUX_MAIN_OUTSEL IOMUX_MAIN_OUTSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IOMUX_MAIN_OENSEL

IOMux Main Function Output Enable Select Register
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOMUX_MAIN_OENSEL IOMUX_MAIN_OENSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CLK_BBGEN_DIV_CLK

BBGEN Divider Clock
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_BBGEN_DIV_CLK CLK_BBGEN_DIV_CLK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BBGEN_DIV

BBGEN_DIV : Bbgen divider value
bits : 0 - 7 (8 bit)


IOMUX_MAIN_DEFAULT_IN

IOMux Main Function Input Default Data Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOMUX_MAIN_DEFAULT_IN IOMUX_MAIN_DEFAULT_IN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IOMUX_ALTF1_INSEL

IOMux Alternate Function 1 Input Data Select Register
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOMUX_ALTF1_INSEL IOMUX_ALTF1_INSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IOMUX_ALTF1_OUTSEL

IOMux Alternate Function 1 Output Data Select Register
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOMUX_ALTF1_OUTSEL IOMUX_ALTF1_OUTSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IOMUX_ALTF1_OENSEL

IOMux Alternate Function 1 Output Enable Select Register
address_offset : 0x98 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOMUX_ALTF1_OENSEL IOMUX_ALTF1_OENSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IOMUX_ALTF1_DEFAULT_IN

IOMux Alternate Function 1 Input Default Data Register
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOMUX_ALTF1_DEFAULT_IN IOMUX_ALTF1_DEFAULT_IN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IOMUX_ALTF2_INSEL

IOMux Alternate Function 2 Input Data Select Register
address_offset : 0xA8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOMUX_ALTF2_INSEL IOMUX_ALTF2_INSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IOMUX_ALTF2_OUTSEL

IOMux Alternate Function 2 Output Data Select Register
address_offset : 0xB0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOMUX_ALTF2_OUTSEL IOMUX_ALTF2_OUTSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IOMUX_ALTF2_OENSEL

IOMux Alternate Function 2 Output Enable Select Register
address_offset : 0xB8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOMUX_ALTF2_OENSEL IOMUX_ALTF2_OENSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IOMUX_ALTF2_DEFAULT_IN

IOMux Alternate Function 1 Input Default Data Register
address_offset : 0xC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOMUX_ALTF2_DEFAULT_IN IOMUX_ALTF2_DEFAULT_IN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IOMUX_ALTF3_INSEL

IOMux Alternate Function 3 Input Data Select Register
address_offset : 0xC8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOMUX_ALTF3_INSEL IOMUX_ALTF3_INSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IOMUX_ALTF3_OUTSEL

IOMux Alternate Function 3 Output Data Select Register
address_offset : 0xD0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOMUX_ALTF3_OUTSEL IOMUX_ALTF3_OUTSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IOMUX_ALTF3_OENSEL

IOMux Alternate Function 3 Output Enable Select Register
address_offset : 0xD8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOMUX_ALTF3_OENSEL IOMUX_ALTF3_OENSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IOMUX_ALTF3_DEFAULT_IN

IOMux Alternate Function 1 Input Default Data Register
address_offset : 0xE0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOMUX_ALTF3_DEFAULT_IN IOMUX_ALTF3_DEFAULT_IN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IOPAD_DS0

IO Pad Drive Select 0 Register
address_offset : 0xE8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOPAD_DS0 IOPAD_DS0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IOPAD_DS1

IO Pad Drive Select 1 Register
address_offset : 0xF0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOPAD_DS1 IOPAD_DS1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IOPAD_PE

IO Pad Pull Enable Register
address_offset : 0xF8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOPAD_PE IOPAD_PE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.