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MPC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL

BLK_MAX

BLK_CFG

BLK_IDX

BLK_LUT

INT_STAT

INT_CLEAR

INT_EN

INT_INFO1

INT_INFO2

INT_SET


CTRL

MPC Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit[4] bit[6] bit[7] bit[8] bit[31]

bit[4] : Security error response configuration
bits : 4 - 8 (5 bit)

Enumeration:

0 : RAZ-WI

Read-As-Zero - Writes ignored

1 : BUSERROR

Bus Error

End of enumeration elements list.

bit[6] : Data interface gating request
bits : 6 - 12 (7 bit)

bit[7] : Data interface gating acknowledge (RO)
bits : 7 - 14 (8 bit)

bit[8] : Auto-increment
bits : 8 - 16 (9 bit)

bit[31] : Security lockdown
bits : 31 - 62 (32 bit)


BLK_MAX

Maximum value of block based index Register
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BLK_MAX BLK_MAX read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit[3_0] bit[31]

bit[3_0] : Block size
bits : 0 - 3 (4 bit)

bit[31] : Initialization in progress
bits : 31 - 62 (32 bit)


BLK_CFG

Block Configuration
address_offset : 0x14 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BLK_CFG BLK_CFG read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BLK_IDX

Index value for accessing block based look up table
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK_IDX BLK_IDX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BLK_LUT

Block based gating Look Up Table
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK_LUT BLK_LUT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

INT_STAT

Interrupt state
address_offset : 0x20 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INT_STAT INT_STAT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit[0]

bit[0] : mpc_irq triggered
bits : 0 - 0 (1 bit)


INT_CLEAR

Interrupt clear
address_offset : 0x24 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

INT_CLEAR INT_CLEAR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit[0]

bit[0] : mpc_irq clear (cleared automatically)
bits : 0 - 0 (1 bit)


INT_EN

Interrupt enable
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_EN INT_EN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit[0]

bit[0] : mpc_irq enable. Bits are valid when mpc_irq triggered is set
bits : 0 - 0 (1 bit)


INT_INFO1

Interrupt information 1
address_offset : 0x2C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INT_INFO1 INT_INFO1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

INT_INFO2

Interrupt information 2
address_offset : 0x30 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INT_INFO2 INT_INFO2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit[15_0] bit[16] bit[17]

bit[15_0] : hmaster
bits : 0 - 15 (16 bit)

bit[16] : hnonsec
bits : 16 - 32 (17 bit)

bit[17] : cfg_ns
bits : 17 - 34 (18 bit)


INT_SET

Interrupt set. Debug purpose only
address_offset : 0x34 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

INT_SET INT_SET write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit[0]

bit[0] : mpc_irq set. Debug purpose only
bits : 0 - 0 (1 bit)



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