\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
MPC Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
bit[4] : Security error response configuration
bits : 4 - 8 (5 bit)
Enumeration:
0 : RAZ-WI
Read-As-Zero - Writes ignored
1 : BUSERROR
Bus Error
End of enumeration elements list.
bit[6] : Data interface gating request
bits : 6 - 12 (7 bit)
bit[7] : Data interface gating acknowledge (RO)
bits : 7 - 14 (8 bit)
bit[8] : Auto-increment
bits : 8 - 16 (9 bit)
bit[31] : Security lockdown
bits : 31 - 62 (32 bit)
Maximum value of block based index Register
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
bit[3_0] : Block size
bits : 0 - 3 (4 bit)
bit[31] : Initialization in progress
bits : 31 - 62 (32 bit)
Block Configuration
address_offset : 0x14 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Index value for accessing block based look up table
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Block based gating Look Up Table
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Interrupt state
address_offset : 0x20 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
bit[0] : mpc_irq triggered
bits : 0 - 0 (1 bit)
Interrupt clear
address_offset : 0x24 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
bit[0] : mpc_irq clear (cleared automatically)
bits : 0 - 0 (1 bit)
Interrupt enable
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
bit[0] : mpc_irq enable. Bits are valid when mpc_irq triggered is set
bits : 0 - 0 (1 bit)
Interrupt information 1
address_offset : 0x2C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Interrupt information 2
address_offset : 0x30 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
bit[15_0] : hmaster
bits : 0 - 15 (16 bit)
bit[16] : hnonsec
bits : 16 - 32 (17 bit)
bit[17] : cfg_ns
bits : 17 - 34 (18 bit)
Interrupt set. Debug purpose only
address_offset : 0x34 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
bit[0] : mpc_irq set. Debug purpose only
bits : 0 - 0 (1 bit)
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