WATCHDOG

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xC04 byte (0x0)
mem_usage : registers
protection : not protected

Registers

WDOGLOAD

WDOGRIS

WDOGMIS

WDOGVALUE

WDOGCONTROL

WDOGINTCLR

WDOGLOCK


WDOGLOAD

Watchdog Load Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

WDOGRIS

Watchdog Raw Interrupt Status Register
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0

read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RIS

RIS : Raw watchdog Interrupt
bits : 0 - 0


WDOGMIS

Watchdog Mask Interrupt Status Register
address_offset : 0x14 Bytes (0x0)
access : read-only
reset_value : 0x0

read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MIS

MIS : Masked Watchdog Interrupt
bits : 0 - 0


WDOGVALUE

Watchdog Value Register
address_offset : 0x4 Bytes (0x0)
access : read-only
reset_value : 0x0

read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

WDOGCONTROL

Watchdog Control Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTEN RESEN

INTEN : Enable the interrupt event
bits : 0 - 0

Enumeration:

0 : Disable

Disable Watchdog interrupt

1 : Enable

Enable Watchdog interrupt.

End of enumeration elements list.

RESEN : Enable watchdog reset output
bits : 1 - 1

Enumeration:

0 : Disable

Disable Watchdog reset

1 : Enable

Enable Watchdog reset

End of enumeration elements list.


WDOGINTCLR

Watchdog Interrupt Clear Register
address_offset : 0xC Bytes (0x0)
access : write-only
reset_value : 0x0

write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT

INT : Interrupt
bits : 0 - 0


WDOGLOCK

Watchdog Lock Register
address_offset : 0xC00 Bytes (0x0)
access : read-write
reset_value : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Status Access

Status : Register write enable status
bits : 0 - 0

Enumeration:

0 : Enabled

Write access to all other registers is enabled. This is the default.

1 : Disabled

Write access to all other registers is disabled.

End of enumeration elements list.

Access : Enable register writes
bits : 1 - 31



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.