\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCC_RESET : Reset Active low
bits : 0 - 0 (1 bit)
GPTIMER_RESET : Reset Active low
bits : 1 - 2 (2 bit)
I2C0_RESET : Reset Active low
bits : 2 - 4 (3 bit)
I2C1_RESET : Reset Active low
bits : 3 - 6 (4 bit)
I2S_RESET : Reset Active low
bits : 4 - 8 (5 bit)
SPI_RESET : Reset Active low
bits : 5 - 10 (6 bit)
QSPI_RESET : Reset Active low
bits : 6 - 12 (7 bit)
UART0_RESET : Reset Active low
bits : 7 - 14 (8 bit)
UART1_RESET : Reset Active low
bits : 8 - 16 (9 bit)
GPIO_RESET : Reset Active low
bits : 9 - 18 (10 bit)
PVT_RESET : Reset Active low
bits : 10 - 20 (11 bit)
PWM0_RESET : Reset Active low
bits : 11 - 22 (12 bit)
PWM1_RESET : Reset Active low
bits : 12 - 24 (13 bit)
PWM2_RESET : Reset Active low
bits : 13 - 26 (14 bit)
RTC_RESET : Reset Active low
bits : 14 - 28 (15 bit)
RFE_RFI_RESET : Reset Active low
bits : 15 - 30 (16 bit)
OTP_RESET : Reset Active low
bits : 16 - 32 (17 bit)
OTP_PSEL_ENABLE : PSEL enable
bits : 17 - 34 (18 bit)
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBGENIN : DBGENIN
bits : 0 - 0 (1 bit)
NIDENIN : NIDENIN
bits : 1 - 2 (2 bit)
SPIDENIN : SPIDENIN
bits : 2 - 4 (3 bit)
SPNIDENIN : SPNIDENIN
bits : 3 - 6 (4 bit)
LLCDBGENIN : LLCDBGENIN
bits : 4 - 8 (5 bit)
dbg_dcu_force : 0: use Crypto DCU 1: Use SCC signal
bits : 31 - 62 (32 bit)
Power gate enable of SRAM blocks
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ahb_ppc_irq_enable : ahb_ppc_irq_enable
bits : 0 - 0 (1 bit)
reserved : reserved
bits : 1 - 2 (2 bit)
qspi_mpc_irq_enable : qspi_mpc_irq_enable
bits : 2 - 4 (3 bit)
qspi_mpc_irq_clear : qspi_mpc_irq_clear
bits : 3 - 6 (4 bit)
sram_mpc_irq_enable : sram_mpc_irq_enable
bits : 4 - 8 (5 bit)
sram_mpc_irq_clear : sram_mpc_irq_clear
bits : 5 - 10 (6 bit)
Reset vector for CPU0 Secure Mode
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Reset vector for CPU1 Secure Mode
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IO Main Function Input Data Select
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
main_func_idata_sel : 1: Main function of corresponding IO Selected
bits : 0 - 31 (32 bit)
IO Main Function Output Data Select
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
main_func_odata_sel : 1: Main function of corresponding IO Selected
bits : 0 - 31 (32 bit)
IO Main Function Output Enable Select
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
main_func_outen_sel : 1: Main function OEN Selected
bits : 0 - 31 (32 bit)
Default In value to main function IPs when main function is not selected
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
clk_main_sel : clk_main_selw
bits : 0 - 1 (2 bit)
clk_main_en : Clock main enable
bits : 2 - 4 (3 bit)
clk_scc_en : Clock scc enable
bits : 3 - 6 (4 bit)
clk_ref_sel : 0: REFCLK 1: FASTCLK
bits : 4 - 8 (5 bit)
clk_ref_en : Clock ref enable
bits : 5 - 10 (6 bit)
clk_scc_sel : 0: SCCCLK 1: FASTCLK
bits : 6 - 12 (7 bit)
clk_pll_in_sel : 0: Pad 32K REFCLK 1: Reserved
bits : 7 - 14 (8 bit)
Reserved : Reserved
bits : 8 - 19 (12 bit)
clk_test_sel : Reset Active low
bits : 12 - 26 (15 bit)
Enumeration:
0 : PLLVCOCLK
PLLVCOCLK
1 : FCLK
FCLK
2 : SYSCLK
SYSCLK
3 : RM_CLK32K
RM_CLK32K
4 : RM_CLK32M
RM_CLK32M
5 : SCCCLK
SCCCLK
End of enumeration elements list.
clk_test_en : Test clock enable
bits : 15 - 30 (16 bit)
clk_dap_en : DAP clock enable
bits : 16 - 32 (17 bit)
clk_llc_dap_en : LLC DAP clock enable
bits : 17 - 34 (18 bit)
IO Alt Function1 Input Data Select
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
alt_func1_idata_sel : 1: Alt function1 of corresponding IO Selected
bits : 0 - 31 (32 bit)
IO Alt Function1 Output Data Select
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
alt_func1_odata_sel : 1: Alt function1 of corresponding IO Selected
bits : 0 - 31 (32 bit)
IO Alt Function1 Output Enable Select
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
alt_func1_outen_sel : 1: Alt function1 OEN Selected
bits : 0 - 31 (32 bit)
Default In value to Alt Function1 IPs when Alt Function1 is not selected
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IO Alt Function2 Input Data Select
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
alt_func2_idata_sel : 1: Alt function2 of corresponding IO Selected
bits : 0 - 31 (32 bit)
IO Alt Function2 Output Data Select
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
alt_func2_odata_sel : 1: Alt function2 of corresponding IO Selected
bits : 0 - 31 (32 bit)
IO Alt Function2 Output Enable Select
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
alt_func2_outen_sel : 1: Alt function2 OEN Selected
bits : 0 - 31 (32 bit)
Default In value to Alt Function2 IPs when Alt Function2 is not selected
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PVT control register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSTSENNUM : TSTSENNUM
bits : 0 - 4 (5 bit)
TSTGRPSEL : TSTGRPSEL
bits : 5 - 10 (6 bit)
Reserved
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Drive Select0.
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Drive Select1.
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Pull Enable 0: disabled, 1: enabled
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Pull mode select 0: pull down, 1: pull up
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Selw rate 0: slow, 1: fast
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Input mode select 0: cmos, 1: shmitt trigger
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DFT_RAMHOLD : DFT_RAMHOLD
bits : 0 - 0 (1 bit)
DFT_CGEN : DFT_CGEN
bits : 1 - 2 (2 bit)
DFT_RSTDISABLE : DFT_RSTDISABLE
bits : 2 - 5 (4 bit)
DFT_ISODISABLE : DFT_ISODISABLE
bits : 4 - 8 (5 bit)
DFT_PWRUP : DFT_PWRUP
bits : 5 - 10 (6 bit)
DFT_MCPHOLD : DFT_MCPHOLD
bits : 6 - 12 (7 bit)
DFT_FCLKDIVBYPASS : DFT_FCLKDIVBYPASS
bits : 7 - 14 (8 bit)
DFT_SYSCLKDIVBYPASS : DFT_SYSCLKDIVBYPASS
bits : 8 - 16 (9 bit)
Reserved
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PVT control register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTMCHCISBYPASS : 0: Asynchronous, 1: Synchronous
bits : 0 - 0 (1 bit)
CTMCHCIHSBYPASS : 0: Asynchronous, 1: Synchronous
bits : 1 - 5 (5 bit)
DBGENSELDIS : DBGENSELDIS
bits : 5 - 10 (6 bit)
NIDENSELDIS : NIDENSELDIS
bits : 6 - 12 (7 bit)
SPIDENSELDIS : SPIDENSELDIS
bits : 7 - 14 (8 bit)
SPNIDENSELDIS : SPNIDENSELDIS
bits : 8 - 16 (9 bit)
LLCDBGENSELDIS : LLCDBGENSELDIS
bits : 9 - 18 (10 bit)
PVT control register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TISBYPASSIN : TISBYPASSIN
bits : 0 - 7 (8 bit)
TISBYPASSACK : TISBYPASSACK
bits : 8 - 19 (12 bit)
TIHSBYPASS : TIHSBYPASS
bits : 12 - 27 (16 bit)
TINIDENSEL : TINIDENSEL
bits : 16 - 39 (24 bit)
TODBGENSEL : TODBGENSEL
bits : 24 - 51 (28 bit)
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
clk_req_set : clk_req_set
bits : 0 - 0 (1 bit)
pwr_req_set : pwr_req_set
bits : 1 - 5 (5 bit)
pwr_req_set_en : pwr_req_set_en
bits : 8 - 19 (12 bit)
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
clk_req_clear : clk_req_clear
bits : 0 - 0 (1 bit)
pwr_req_clear : pwr_req_clear
bits : 1 - 5 (5 bit)
IO Alt Function3 Input Data Select
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
alt_func3_idata_sel : 1: Alt function3 of corresponding IO Selected
bits : 0 - 31 (32 bit)
IO Alt Function3 Output Data Select
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
alt_func3_odata_sel : 1: Alt function3 of corresponding IO Selected
bits : 0 - 31 (32 bit)
IO Alt Function3 Output Enable Select
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
alt_func3_outen_sel : 1: Alt function3 OEN Selected
bits : 0 - 31 (32 bit)
Default In value to Alt Function3 IPs when Alt Function3 is not selected
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Q-Channels QACTIVE Override
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU0 Isolation Override
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU1 Isolation Override
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU 0 icache sram ldata assist
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU 0 icache sramtag assist
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU 1 icache ldata assist
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU 1 icache sramtag assist
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
pd : Power down for PLL (0: PLL ON, 1: PLL OFF)
bits : 0 - 0 (1 bit)
bypass : FREF is bypassed to FOUT1 and FOUT2
bits : 1 - 2 (2 bit)
foutpostdiv1pd : First post divide power down. (0: ON, 1: OFF)
bits : 2 - 4 (3 bit)
foutpostdiv2pd : Second post divide power down. Not used
bits : 3 - 6 (4 bit)
foutvcopd : VCO rate output clock power down. Not used
bits : 4 - 8 (5 bit)
postdiv1 : irst post divide value (for FOUT1)
bits : 8 - 19 (12 bit)
postdiv2 : Second post divide value (for FOUT2). Not used
bits : 12 - 27 (16 bit)
fbdiv : PLL Feedback divide value
bits : 16 - 45 (30 bit)
System sram assist
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
System sram assist
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Crypto ram pka
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Crypto sec sram
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Reserved
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Power clock request edge select
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Power clock request enable
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
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