QSPI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xB0 byte (0x0)
mem_usage : registers
protection : not protected

Registers

QSPICFG

DEVSIZE

REMAPADDR

DEVREADINSTR

DEVWRITEINSTR

FLASHCMDCTRL

FLASHCMDADDR

FLASHCMDRDATALOW

FLASHCMDRDATAUP

FLASHCMDWRDATALOW

FLASHCMDWRDATAUP


QSPICFG

QSPI Configuration Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QSPIEN CLKPOLARITY CLKPHASE PHYMODEEN Reserved ENDIRACCCTR LEGIPMODEEN PERSELDEC PERCSLINES WPPINDRV ENDMAPIF ENAHBADDRRM
Warning: Undefined array key 33 in /app/public/svg.inc on line 285
ENTRXIPMODEONR
Warning: Undefined array key 35 in /app/public/svg.inc on line 285
ENTRXIPMODEIMM
Warning: Undefined array key 37 in /app/public/svg.inc on line 285
MAMOBRDIV
Warning: Undefined array key 42 in /app/public/svg.inc on line 285
AHBDECEN
Warning: Undefined array key 47 in /app/public/svg.inc on line 285
DTREN
Warning: Undefined array key 49 in /app/public/svg.inc on line 285
PIPLPHYEN
Warning: Undefined array key 51 in /app/public/svg.inc on line 285
Reserved
Warning: Undefined array key 57 in /app/public/svg.inc on line 285
PIPLIDLE
Warning: Undefined array key 63 in /app/public/svg.inc on line 285

QSPIEN : QSPI Enable
bits : 0 - 0

CLKPOLARITY : Clock polarity outside SPI word. This maps to the standard SPI CPOL transfer format
bits : 1 - 2

CLKPHASE : Clock phase, this maps to the standard SPI CPHA transfer format
bits : 2 - 4

PHYMODEEN : PHY Mode enable
bits : 3 - 6

Reserved : Reserved
bits : 4 - 10

ENDIRACCCTR : Enable Direct Access Controller
bits : 7 - 14

LEGIPMODEEN : Legacy IP Mode Enable
bits : 8 - 16

PERSELDEC : Peripheral select decode
bits : 9 - 18

Enumeration:

0 : Disabled

Only 1 of 4 selects n_ss_out is active

1 : Enabled

Allow external 4-to-16 decode

End of enumeration elements list.

PERCSLINES : Peripheral chip select lines
bits : 10 - 23

Enumeration:

0bxxx0 : ss0

n_ss_out: 0b1110

0bxx01 : ss1

n_ss_out: 0b1101

0bx011 : ss2

n_ss_out: 0b1011

0b0111 : ss3

n_ss_out: 0b0111

0b1111 : ssinactive

n_ss_out: 0b1111 (no peripheral selected)

End of enumeration elements list.

WPPINDRV : Set to drive the WP pin of Flash device
bits : 14 - 28

ENDMAPIF : Enable DMA Peripheral Interface
bits : 15 - 30

ENAHBADDRRM : Enable AHB Address Re-mapping
bits : 16 - 32

ENTRXIPMODEONR : Enter XIP Mode on next READ
bits : 17 - 34

ENTRXIPMODEIMM : Enter XIP Mode immediately
bits : 18 - 36

MAMOBRDIV : Master mode baud rate divisor (2 to 32)
bits : 19 - 41

AHBDECEN : Enable AHB Decoder
bits : 23 - 46

DTREN : Enable DTR Protocol
bits : 24 - 48

PIPLPHYEN : Pipeline PHY Mode enable
bits : 25 - 50

Reserved : Reserved
bits : 26 - 56

PIPLIDLE : Serial Interface and QSPI pipeline is IDLE
bits : 31 - 62


DEVSIZE

Device Size Configuration Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRBYTENUM BYTEPERDEVPGNUM BYTEPERBLKNUM
Warning: Undefined array key 37 in /app/public/svg.inc on line 285
FDEVSIZECS0
Warning: Undefined array key 44 in /app/public/svg.inc on line 285
FDEVSIZECS1
Warning: Undefined array key 48 in /app/public/svg.inc on line 285
FDEVSIZECS2
Warning: Undefined array key 52 in /app/public/svg.inc on line 285
FDEVSIZECS3
Warning: Undefined array key 56 in /app/public/svg.inc on line 285
Reserved
Warning: Undefined array key 61 in /app/public/svg.inc on line 285

ADDRBYTENUM : Number of address bytes
bits : 0 - 3

BYTEPERDEVPGNUM : Number of bytes per device page
bits : 4 - 19

BYTEPERBLKNUM : Number of bytes per block
bits : 16 - 36

FDEVSIZECS0 : Size of Flash Device connected to CS[0] pin
bits : 21 - 43

FDEVSIZECS1 : Size of Flash Device connected to CS[1] pin
bits : 23 - 47

FDEVSIZECS2 : Size of Flash Device connected to CS[2] pin
bits : 25 - 51

FDEVSIZECS3 : Size of Flash Device connected to CS[3] pin
bits : 27 - 55

Reserved : Reserved
bits : 29 - 60


REMAPADDR

Remap Address Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DEVREADINSTR

Device Read Instruction Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ROPCODE INSTRTYPE DDRBITEN Reserved ADDRTRTYPESSPI Reserved Reserved DATATRTYPESSPI
Warning: Undefined array key 34 in /app/public/svg.inc on line 285
Reserved
Warning: Undefined array key 38 in /app/public/svg.inc on line 285
MODEBITEN
Warning: Undefined array key 41 in /app/public/svg.inc on line 285
Reserved
Warning: Undefined array key 45 in /app/public/svg.inc on line 285
READDUMCLKCYCNUM
Warning: Undefined array key 53 in /app/public/svg.inc on line 285

ROPCODE : Read Opcode to use when not in XIP mode
bits : 0 - 7

INSTRTYPE : Instruction Type
bits : 8 - 17

DDRBITEN : DDR Bit Enable
bits : 10 - 20

Reserved : Reserved
bits : 11 - 22

ADDRTRTYPESSPI : Address Transfer Type for Standard SPI modes
bits : 12 - 25

Reserved : Reserved
bits : 14 - 29

Reserved : Reserved
bits : 14 - 29

DATATRTYPESSPI : Data Transfer Type for Standard SPI modes
bits : 16 - 33

Reserved : Reserved
bits : 18 - 37

MODEBITEN : Mode Bit Enable
bits : 20 - 40

Reserved : Reserved
bits : 21 - 44

READDUMCLKCYCNUM : Number of Dummy Clock Cycles required by device for Read Instruction
bits : 24 - 52


DEVWRITEINSTR

Device Write Instruction Configuration Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WROPCODE WELDISABLE Reserved ADDRTRTYPESSPI Reserved Reserved DATATRTYPESSPI
Warning: Undefined array key 34 in /app/public/svg.inc on line 285
Reserved
Warning: Undefined array key 42 in /app/public/svg.inc on line 285
WRITEDUMCLKCYCNUM
Warning: Undefined array key 53 in /app/public/svg.inc on line 285

WROPCODE : Write Opcode
bits : 0 - 7

WELDISABLE : WEL Disable
bits : 8 - 16

Reserved : Reserved
bits : 9 - 20

ADDRTRTYPESSPI : Address Transfer Type for Standard SPI modes
bits : 12 - 25

Reserved : Reserved
bits : 14 - 29

Reserved : Reserved
bits : 14 - 29

DATATRTYPESSPI : Data Transfer Type for Standard SPI modes
bits : 16 - 33

Reserved : Reserved
bits : 18 - 41

WRITEDUMCLKCYCNUM : Number of Dummy Clock Cycles required by device for Write Instruction
bits : 24 - 52


FLASHCMDCTRL

Flash Command Control Register
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMDEXEC CMDEXINPROG Reserved DUMCYCNUM WRDATABYTENUM WRDATAEN ADDRBYTENUM
Warning: Undefined array key 34 in /app/public/svg.inc on line 285
MODEBITEN
Warning: Undefined array key 37 in /app/public/svg.inc on line 285
CMDADDREN
Warning: Undefined array key 39 in /app/public/svg.inc on line 285
RDATABYTENUM
Warning: Undefined array key 43 in /app/public/svg.inc on line 285
RDATAEN
Warning: Undefined array key 47 in /app/public/svg.inc on line 285
CMDOPCODE
Warning: Undefined array key 56 in /app/public/svg.inc on line 285

CMDEXEC : Execute the command
bits : 0 - 0

CMDEXINPROG : Command execution in progress
bits : 1 - 2

Reserved : Reserved
bits : 2 - 8

DUMCYCNUM : Number of Dummy Cycles
bits : 7 - 18

WRDATABYTENUM : Number of Write Data Bytes
bits : 12 - 26

WRDATAEN : Write Data Enable
bits : 15 - 30

ADDRBYTENUM : Number of Address Bytes
bits : 16 - 33

MODEBITEN : Mode Bit Enable
bits : 18 - 36

CMDADDREN : Command Address Enable
bits : 19 - 38

RDATABYTENUM : Number of Read Data Bytes
bits : 20 - 42

RDATAEN : Read Data Enable
bits : 23 - 46

CMDOPCODE : Command Opcode
bits : 24 - 55


FLASHCMDADDR

Flash Command Address Register
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FLASHCMDRDATALOW

Flash Command Read Data Register (Lower)
address_offset : 0xA0 Bytes (0x0)
access : read-only
reset_value : 0x0

read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FLASHCMDRDATAUP

Flash Command Read Data Register (Upper)
address_offset : 0xA4 Bytes (0x0)
access : read-only
reset_value : 0x0

read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FLASHCMDWRDATALOW

Flash Command Write Data Register (Lower)
address_offset : 0xA8 Bytes (0x0)
access : read-write
reset_value : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FLASHCMDWRDATAUP

Flash Command Write Data Register (Upper)
address_offset : 0xAC Bytes (0x0)
access : read-write
reset_value : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.