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QSPI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xB0 byte (0x0)
mem_usage : registers
protection : not protected

Registers

QSPICFG

DEVSIZE

REMAPADDR

DEVREADINSTR

DEVWRITEINSTR

FLASHCMDCTRL

FLASHCMDADDR

FLASHCMDRDATALOW

FLASHCMDRDATAUP

FLASHCMDWRDATALOW

FLASHCMDWRDATAUP


QSPICFG

QSPI Configuration Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QSPICFG QSPICFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QSPIEN CLKPOLARITY CLKPHASE PHYMODEEN Reserved ENDIRACCCTR LEGIPMODEEN PERSELDEC PERCSLINES WPPINDRV ENDMAPIF ENAHBADDRRM ENTRXIPMODEONR ENTRXIPMODEIMM MAMOBRDIV AHBDECEN DTREN PIPLPHYEN Reserved PIPLIDLE

QSPIEN : QSPI Enable
bits : 0 - 0 (1 bit)

CLKPOLARITY : Clock polarity outside SPI word. This maps to the standard SPI CPOL transfer format
bits : 1 - 2 (2 bit)

CLKPHASE : Clock phase, this maps to the standard SPI CPHA transfer format
bits : 2 - 4 (3 bit)

PHYMODEEN : PHY Mode enable
bits : 3 - 6 (4 bit)

Reserved : Reserved
bits : 4 - 10 (7 bit)

ENDIRACCCTR : Enable Direct Access Controller
bits : 7 - 14 (8 bit)

LEGIPMODEEN : Legacy IP Mode Enable
bits : 8 - 16 (9 bit)

PERSELDEC : Peripheral select decode
bits : 9 - 18 (10 bit)

Enumeration:

0 : Disabled

Only 1 of 4 selects n_ss_out is active

1 : Enabled

Allow external 4-to-16 decode

End of enumeration elements list.

PERCSLINES : Peripheral chip select lines
bits : 10 - 23 (14 bit)

Enumeration:

0bxxx0 : ss0

n_ss_out: 0b1110

0bxx01 : ss1

n_ss_out: 0b1101

0bx011 : ss2

n_ss_out: 0b1011

0b0111 : ss3

n_ss_out: 0b0111

0b1111 : ssinactive

n_ss_out: 0b1111 (no peripheral selected)

End of enumeration elements list.

WPPINDRV : Set to drive the WP pin of Flash device
bits : 14 - 28 (15 bit)

ENDMAPIF : Enable DMA Peripheral Interface
bits : 15 - 30 (16 bit)

ENAHBADDRRM : Enable AHB Address Re-mapping
bits : 16 - 32 (17 bit)

ENTRXIPMODEONR : Enter XIP Mode on next READ
bits : 17 - 34 (18 bit)

ENTRXIPMODEIMM : Enter XIP Mode immediately
bits : 18 - 36 (19 bit)

MAMOBRDIV : Master mode baud rate divisor (2 to 32)
bits : 19 - 41 (23 bit)

AHBDECEN : Enable AHB Decoder
bits : 23 - 46 (24 bit)

DTREN : Enable DTR Protocol
bits : 24 - 48 (25 bit)

PIPLPHYEN : Pipeline PHY Mode enable
bits : 25 - 50 (26 bit)

Reserved : Reserved
bits : 26 - 56 (31 bit)

PIPLIDLE : Serial Interface and QSPI pipeline is IDLE
bits : 31 - 62 (32 bit)


DEVSIZE

Device Size Configuration Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVSIZE DEVSIZE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRBYTENUM BYTEPERDEVPGNUM BYTEPERBLKNUM FDEVSIZECS0 FDEVSIZECS1 FDEVSIZECS2 FDEVSIZECS3 Reserved

ADDRBYTENUM : Number of address bytes
bits : 0 - 3 (4 bit)

BYTEPERDEVPGNUM : Number of bytes per device page
bits : 4 - 19 (16 bit)

BYTEPERBLKNUM : Number of bytes per block
bits : 16 - 36 (21 bit)

FDEVSIZECS0 : Size of Flash Device connected to CS[0] pin
bits : 21 - 43 (23 bit)

FDEVSIZECS1 : Size of Flash Device connected to CS[1] pin
bits : 23 - 47 (25 bit)

FDEVSIZECS2 : Size of Flash Device connected to CS[2] pin
bits : 25 - 51 (27 bit)

FDEVSIZECS3 : Size of Flash Device connected to CS[3] pin
bits : 27 - 55 (29 bit)

Reserved : Reserved
bits : 29 - 60 (32 bit)


REMAPADDR

Remap Address Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REMAPADDR REMAPADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DEVREADINSTR

Device Read Instruction Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVREADINSTR DEVREADINSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ROPCODE INSTRTYPE DDRBITEN Reserved ADDRTRTYPESSPI Reserved Reserved DATATRTYPESSPI Reserved MODEBITEN Reserved READDUMCLKCYCNUM

ROPCODE : Read Opcode to use when not in XIP mode
bits : 0 - 7 (8 bit)

INSTRTYPE : Instruction Type
bits : 8 - 17 (10 bit)

DDRBITEN : DDR Bit Enable
bits : 10 - 20 (11 bit)

Reserved : Reserved
bits : 11 - 22 (12 bit)

ADDRTRTYPESSPI : Address Transfer Type for Standard SPI modes
bits : 12 - 25 (14 bit)

Reserved : Reserved
bits : 14 - 29 (16 bit)

Reserved : Reserved
bits : 14 - 29 (16 bit)

DATATRTYPESSPI : Data Transfer Type for Standard SPI modes
bits : 16 - 33 (18 bit)

Reserved : Reserved
bits : 18 - 37 (20 bit)

MODEBITEN : Mode Bit Enable
bits : 20 - 40 (21 bit)

Reserved : Reserved
bits : 21 - 44 (24 bit)

READDUMCLKCYCNUM : Number of Dummy Clock Cycles required by device for Read Instruction
bits : 24 - 52 (29 bit)


DEVWRITEINSTR

Device Write Instruction Configuration Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVWRITEINSTR DEVWRITEINSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WROPCODE WELDISABLE Reserved ADDRTRTYPESSPI Reserved Reserved DATATRTYPESSPI Reserved WRITEDUMCLKCYCNUM

WROPCODE : Write Opcode
bits : 0 - 7 (8 bit)

WELDISABLE : WEL Disable
bits : 8 - 16 (9 bit)

Reserved : Reserved
bits : 9 - 20 (12 bit)

ADDRTRTYPESSPI : Address Transfer Type for Standard SPI modes
bits : 12 - 25 (14 bit)

Reserved : Reserved
bits : 14 - 29 (16 bit)

Reserved : Reserved
bits : 14 - 29 (16 bit)

DATATRTYPESSPI : Data Transfer Type for Standard SPI modes
bits : 16 - 33 (18 bit)

Reserved : Reserved
bits : 18 - 41 (24 bit)

WRITEDUMCLKCYCNUM : Number of Dummy Clock Cycles required by device for Write Instruction
bits : 24 - 52 (29 bit)


FLASHCMDCTRL

Flash Command Control Register
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FLASHCMDCTRL FLASHCMDCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMDEXEC CMDEXINPROG Reserved DUMCYCNUM WRDATABYTENUM WRDATAEN ADDRBYTENUM MODEBITEN CMDADDREN RDATABYTENUM RDATAEN CMDOPCODE

CMDEXEC : Execute the command
bits : 0 - 0 (1 bit)

CMDEXINPROG : Command execution in progress
bits : 1 - 2 (2 bit)

Reserved : Reserved
bits : 2 - 8 (7 bit)

DUMCYCNUM : Number of Dummy Cycles
bits : 7 - 18 (12 bit)

WRDATABYTENUM : Number of Write Data Bytes
bits : 12 - 26 (15 bit)

WRDATAEN : Write Data Enable
bits : 15 - 30 (16 bit)

ADDRBYTENUM : Number of Address Bytes
bits : 16 - 33 (18 bit)

MODEBITEN : Mode Bit Enable
bits : 18 - 36 (19 bit)

CMDADDREN : Command Address Enable
bits : 19 - 38 (20 bit)

RDATABYTENUM : Number of Read Data Bytes
bits : 20 - 42 (23 bit)

RDATAEN : Read Data Enable
bits : 23 - 46 (24 bit)

CMDOPCODE : Command Opcode
bits : 24 - 55 (32 bit)


FLASHCMDADDR

Flash Command Address Register
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FLASHCMDADDR FLASHCMDADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FLASHCMDRDATALOW

Flash Command Read Data Register (Lower)
address_offset : 0xA0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FLASHCMDRDATALOW FLASHCMDRDATALOW read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FLASHCMDRDATAUP

Flash Command Read Data Register (Upper)
address_offset : 0xA4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FLASHCMDRDATAUP FLASHCMDRDATAUP read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FLASHCMDWRDATALOW

Flash Command Write Data Register (Lower)
address_offset : 0xA8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FLASHCMDWRDATALOW FLASHCMDWRDATALOW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FLASHCMDWRDATAUP

Flash Command Write Data Register (Upper)
address_offset : 0xAC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FLASHCMDWRDATAUP FLASHCMDWRDATAUP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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