Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
MDMA Global Interrupt/Status Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
GIF0 : Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx)
bits : 0 - 0 (1 bit)
GIF1 : Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx)
bits : 1 - 1 (1 bit)
GIF2 : Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx)
bits : 2 - 2 (1 bit)
GIF3 : Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx)
bits : 3 - 3 (1 bit)
GIF4 : Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx)
bits : 4 - 4 (1 bit)
GIF5 : Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx)
bits : 5 - 5 (1 bit)
GIF6 : Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx)
bits : 6 - 6 (1 bit)
GIF7 : Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx)
bits : 7 - 7 (1 bit)
GIF8 : Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx)
bits : 8 - 8 (1 bit)
GIF9 : Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx)
bits : 9 - 9 (1 bit)
GIF10 : Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx)
bits : 10 - 10 (1 bit)
GIF11 : Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx)
bits : 11 - 11 (1 bit)
GIF12 : Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx)
bits : 12 - 12 (1 bit)
GIF13 : Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx)
bits : 13 - 13 (1 bit)
GIF14 : Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx)
bits : 14 - 14 (1 bit)
GIF15 : Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx)
bits : 15 - 15 (1 bit)
MDMA channel x interrupt/status register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF3 : Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
bits : 0 - 0 (1 bit)
CTCIF3 : Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0.
bits : 1 - 1 (1 bit)
BRTIF3 : Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
bits : 2 - 2 (1 bit)
BTIF3 : Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
bits : 3 - 3 (1 bit)
TCIF3 : channel x buffer transfer complete
bits : 4 - 4 (1 bit)
CRQA3 : channel x request active flag
bits : 16 - 16 (1 bit)
MDMA channel x interrupt flag clear register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CTEIF3 : Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register
bits : 0 - 0 (1 bit)
CCTCIF3 : Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register
bits : 1 - 1 (1 bit)
CBRTIF3 : Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register
bits : 2 - 2 (1 bit)
CBTIF3 : Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register
bits : 3 - 3 (1 bit)
CLTCIF3 : CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register
bits : 4 - 4 (1 bit)
MDMA Channel x error status register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error.
bits : 0 - 6 (7 bit)
TED : Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error.
bits : 7 - 7 (1 bit)
TELD : Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 8 - 8 (1 bit)
TEMD : Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 9 - 9 (1 bit)
ASE : Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 10 - 10 (1 bit)
BSE : Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 11 - 11 (1 bit)
This register is used to control the concerned channel.
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : channel enable
bits : 0 - 0 (1 bit)
access : read-write
TEIE : Transfer error interrupt enable This bit is set and cleared by software.
bits : 1 - 1 (1 bit)
access : read-write
CTCIE : Channel Transfer Complete interrupt enable This bit is set and cleared by software.
bits : 2 - 2 (1 bit)
access : read-write
BRTIE : Block Repeat transfer interrupt enable This bit is set and cleared by software.
bits : 3 - 3 (1 bit)
access : read-write
BTIE : Block Transfer interrupt enable This bit is set and cleared by software.
bits : 4 - 4 (1 bit)
access : read-write
TCIE : buffer Transfer Complete interrupt enable This bit is set and cleared by software.
bits : 5 - 5 (1 bit)
access : read-write
PL : Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0.
bits : 6 - 7 (2 bit)
access : read-write
BEX : byte Endianness exchange
bits : 12 - 12 (1 bit)
access : read-write
HEX : Half word Endianes exchange
bits : 13 - 13 (1 bit)
access : read-write
WEX : Word Endianness exchange
bits : 14 - 14 (1 bit)
access : read-write
SWRQ : SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access).
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel.
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
bits : 0 - 1 (2 bit)
DINC : Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden.
bits : 2 - 3 (2 bit)
SSIZE : Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS < SSIZE and SINC ≠ 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1).
bits : 4 - 5 (2 bit)
DSIZE : Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS < DSIZE and DINC ≠ 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1).
bits : 6 - 7 (2 bit)
SINCOS : source increment offset size
bits : 8 - 9 (2 bit)
DINCOS : Destination increment offset
bits : 10 - 11 (2 bit)
SBURST : source burst transfer configuration
bits : 12 - 14 (3 bit)
DBURST : Destination burst transfer configuration
bits : 15 - 17 (3 bit)
TLEN : buffer transfer lengh
bits : 18 - 24 (7 bit)
PKE : PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0
bits : 25 - 25 (1 bit)
PAM : Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0
bits : 26 - 27 (2 bit)
TRGM : Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0.
bits : 28 - 29 (2 bit)
SWRM : SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0.
bits : 30 - 30 (1 bit)
BWM : Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable.
bits : 31 - 31 (1 bit)
MDMA Channel x block number of data register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : block number of data to transfer
bits : 0 - 16 (17 bit)
BRSUM : Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0.
bits : 18 - 18 (1 bit)
BRDUM : Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0.
bits : 19 - 19 (1 bit)
BRC : Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0.
bits : 20 - 31 (12 bit)
MDMA channel x source address register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : source adr base
bits : 0 - 31 (32 bit)
MDMA channel x destination address register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : Destination adr base
bits : 0 - 31 (32 bit)
MDMA channel x Block Repeat address Update register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : source adresse update value
bits : 0 - 15 (16 bit)
DUV : destination address update
bits : 16 - 31 (16 bit)
MDMA channel x Link Address register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : Link address register
bits : 0 - 31 (32 bit)
MDMA channel x Trigger and Bus selection Register
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : Trigger selection
bits : 0 - 5 (6 bit)
SBUS : Source BUS select This bit is protected and can be written only if EN is 0.
bits : 16 - 16 (1 bit)
DBUS : Destination BUS slect This bit is protected and can be written only if EN is 0.
bits : 17 - 17 (1 bit)
MDMA channel x Mask address register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : Mask address
bits : 0 - 31 (32 bit)
MDMA channel x Mask Data register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : Mask data
bits : 0 - 31 (32 bit)
MDMA channel x interrupt/status register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF4 : Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
bits : 0 - 0 (1 bit)
CTCIF4 : Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0.
bits : 1 - 1 (1 bit)
BRTIF4 : Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
bits : 2 - 2 (1 bit)
BTIF4 : Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
bits : 3 - 3 (1 bit)
TCIF4 : channel x buffer transfer complete
bits : 4 - 4 (1 bit)
CRQA4 : channel x request active flag
bits : 16 - 16 (1 bit)
MDMA channel x interrupt flag clear register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CTEIF4 : Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register
bits : 0 - 0 (1 bit)
CCTCIF4 : Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register
bits : 1 - 1 (1 bit)
CBRTIF4 : Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register
bits : 2 - 2 (1 bit)
CBTIF4 : Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register
bits : 3 - 3 (1 bit)
CLTCIF4 : CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register
bits : 4 - 4 (1 bit)
MDMA Channel x error status register
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error.
bits : 0 - 6 (7 bit)
TED : Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error.
bits : 7 - 7 (1 bit)
TELD : Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 8 - 8 (1 bit)
TEMD : Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 9 - 9 (1 bit)
ASE : Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 10 - 10 (1 bit)
BSE : Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 11 - 11 (1 bit)
This register is used to control the concerned channel.
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : channel enable
bits : 0 - 0 (1 bit)
access : read-write
TEIE : Transfer error interrupt enable This bit is set and cleared by software.
bits : 1 - 1 (1 bit)
access : read-write
CTCIE : Channel Transfer Complete interrupt enable This bit is set and cleared by software.
bits : 2 - 2 (1 bit)
access : read-write
BRTIE : Block Repeat transfer interrupt enable This bit is set and cleared by software.
bits : 3 - 3 (1 bit)
access : read-write
BTIE : Block Transfer interrupt enable This bit is set and cleared by software.
bits : 4 - 4 (1 bit)
access : read-write
TCIE : buffer Transfer Complete interrupt enable This bit is set and cleared by software.
bits : 5 - 5 (1 bit)
access : read-write
PL : Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0.
bits : 6 - 7 (2 bit)
access : read-write
BEX : byte Endianness exchange
bits : 12 - 12 (1 bit)
access : read-write
HEX : Half word Endianes exchange
bits : 13 - 13 (1 bit)
access : read-write
WEX : Word Endianness exchange
bits : 14 - 14 (1 bit)
access : read-write
SWRQ : SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access).
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel.
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
bits : 0 - 1 (2 bit)
DINC : Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden.
bits : 2 - 3 (2 bit)
SSIZE : Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS < SSIZE and SINC ≠ 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1).
bits : 4 - 5 (2 bit)
DSIZE : Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS < DSIZE and DINC ≠ 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1).
bits : 6 - 7 (2 bit)
SINCOS : source increment offset size
bits : 8 - 9 (2 bit)
DINCOS : Destination increment offset
bits : 10 - 11 (2 bit)
SBURST : source burst transfer configuration
bits : 12 - 14 (3 bit)
DBURST : Destination burst transfer configuration
bits : 15 - 17 (3 bit)
TLEN : buffer transfer lengh
bits : 18 - 24 (7 bit)
PKE : PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0
bits : 25 - 25 (1 bit)
PAM : Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0
bits : 26 - 27 (2 bit)
TRGM : Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0.
bits : 28 - 29 (2 bit)
SWRM : SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0.
bits : 30 - 30 (1 bit)
BWM : Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable.
bits : 31 - 31 (1 bit)
MDMA Channel x block number of data register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : block number of data to transfer
bits : 0 - 16 (17 bit)
BRSUM : Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0.
bits : 18 - 18 (1 bit)
BRDUM : Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0.
bits : 19 - 19 (1 bit)
BRC : Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0.
bits : 20 - 31 (12 bit)
MDMA channel x source address register
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : source adr base
bits : 0 - 31 (32 bit)
MDMA channel x destination address register
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : Destination adr base
bits : 0 - 31 (32 bit)
MDMA channel x Block Repeat address Update register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : source adresse update value
bits : 0 - 15 (16 bit)
DUV : destination address update
bits : 16 - 31 (16 bit)
MDMA channel x Link Address register
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : Link address register
bits : 0 - 31 (32 bit)
MDMA channel x Trigger and Bus selection Register
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : Trigger selection
bits : 0 - 5 (6 bit)
SBUS : Source BUS select This bit is protected and can be written only if EN is 0.
bits : 16 - 16 (1 bit)
DBUS : Destination BUS slect This bit is protected and can be written only if EN is 0.
bits : 17 - 17 (1 bit)
MDMA channel x Mask address register
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : Mask address
bits : 0 - 31 (32 bit)
MDMA channel x Mask Data register
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : Mask data
bits : 0 - 31 (32 bit)
MDMA channel x interrupt/status register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF5 : Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
bits : 0 - 0 (1 bit)
CTCIF5 : Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0.
bits : 1 - 1 (1 bit)
BRTIF5 : Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
bits : 2 - 2 (1 bit)
BTIF5 : Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
bits : 3 - 3 (1 bit)
TCIF5 : channel x buffer transfer complete
bits : 4 - 4 (1 bit)
CRQA5 : channel x request active flag
bits : 16 - 16 (1 bit)
MDMA channel x interrupt flag clear register
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CTEIF5 : Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register
bits : 0 - 0 (1 bit)
CCTCIF5 : Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register
bits : 1 - 1 (1 bit)
CBRTIF5 : Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register
bits : 2 - 2 (1 bit)
CBTIF5 : Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register
bits : 3 - 3 (1 bit)
CLTCIF5 : CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register
bits : 4 - 4 (1 bit)
MDMA Channel x error status register
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error.
bits : 0 - 6 (7 bit)
TED : Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error.
bits : 7 - 7 (1 bit)
TELD : Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 8 - 8 (1 bit)
TEMD : Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 9 - 9 (1 bit)
ASE : Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 10 - 10 (1 bit)
BSE : Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 11 - 11 (1 bit)
This register is used to control the concerned channel.
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : channel enable
bits : 0 - 0 (1 bit)
access : read-write
TEIE : Transfer error interrupt enable This bit is set and cleared by software.
bits : 1 - 1 (1 bit)
access : read-write
CTCIE : Channel Transfer Complete interrupt enable This bit is set and cleared by software.
bits : 2 - 2 (1 bit)
access : read-write
BRTIE : Block Repeat transfer interrupt enable This bit is set and cleared by software.
bits : 3 - 3 (1 bit)
access : read-write
BTIE : Block Transfer interrupt enable This bit is set and cleared by software.
bits : 4 - 4 (1 bit)
access : read-write
TCIE : buffer Transfer Complete interrupt enable This bit is set and cleared by software.
bits : 5 - 5 (1 bit)
access : read-write
PL : Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0.
bits : 6 - 7 (2 bit)
access : read-write
BEX : byte Endianness exchange
bits : 12 - 12 (1 bit)
access : read-write
HEX : Half word Endianes exchange
bits : 13 - 13 (1 bit)
access : read-write
WEX : Word Endianness exchange
bits : 14 - 14 (1 bit)
access : read-write
SWRQ : SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access).
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel.
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
bits : 0 - 1 (2 bit)
DINC : Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden.
bits : 2 - 3 (2 bit)
SSIZE : Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS < SSIZE and SINC ≠ 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1).
bits : 4 - 5 (2 bit)
DSIZE : Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS < DSIZE and DINC ≠ 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1).
bits : 6 - 7 (2 bit)
SINCOS : source increment offset size
bits : 8 - 9 (2 bit)
DINCOS : Destination increment offset
bits : 10 - 11 (2 bit)
SBURST : source burst transfer configuration
bits : 12 - 14 (3 bit)
DBURST : Destination burst transfer configuration
bits : 15 - 17 (3 bit)
TLEN : buffer transfer lengh
bits : 18 - 24 (7 bit)
PKE : PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0
bits : 25 - 25 (1 bit)
PAM : Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0
bits : 26 - 27 (2 bit)
TRGM : Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0.
bits : 28 - 29 (2 bit)
SWRM : SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0.
bits : 30 - 30 (1 bit)
BWM : Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable.
bits : 31 - 31 (1 bit)
MDMA Channel x block number of data register
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : block number of data to transfer
bits : 0 - 16 (17 bit)
BRSUM : Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0.
bits : 18 - 18 (1 bit)
BRDUM : Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0.
bits : 19 - 19 (1 bit)
BRC : Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0.
bits : 20 - 31 (12 bit)
MDMA channel x source address register
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : source adr base
bits : 0 - 31 (32 bit)
MDMA channel x destination address register
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : Destination adr base
bits : 0 - 31 (32 bit)
MDMA channel x Block Repeat address Update register
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : source adresse update value
bits : 0 - 15 (16 bit)
DUV : destination address update
bits : 16 - 31 (16 bit)
MDMA channel x Link Address register
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : Link address register
bits : 0 - 31 (32 bit)
MDMA channel x Trigger and Bus selection Register
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : Trigger selection
bits : 0 - 5 (6 bit)
SBUS : Source BUS select This bit is protected and can be written only if EN is 0.
bits : 16 - 16 (1 bit)
DBUS : Destination BUS slect This bit is protected and can be written only if EN is 0.
bits : 17 - 17 (1 bit)
MDMA channel x Mask address register
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : Mask address
bits : 0 - 31 (32 bit)
MDMA channel x Mask Data register
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : Mask data
bits : 0 - 31 (32 bit)
MDMA channel x interrupt/status register
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF6 : Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
bits : 0 - 0 (1 bit)
CTCIF6 : Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0.
bits : 1 - 1 (1 bit)
BRTIF6 : Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
bits : 2 - 2 (1 bit)
BTIF6 : Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
bits : 3 - 3 (1 bit)
TCIF6 : channel x buffer transfer complete
bits : 4 - 4 (1 bit)
CRQA6 : channel x request active flag
bits : 16 - 16 (1 bit)
MDMA channel x interrupt flag clear register
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CTEIF6 : Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register
bits : 0 - 0 (1 bit)
CCTCIF6 : Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register
bits : 1 - 1 (1 bit)
CBRTIF6 : Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register
bits : 2 - 2 (1 bit)
CBTIF6 : Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register
bits : 3 - 3 (1 bit)
CLTCIF6 : CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register
bits : 4 - 4 (1 bit)
MDMA Channel x error status register
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error.
bits : 0 - 6 (7 bit)
TED : Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error.
bits : 7 - 7 (1 bit)
TELD : Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 8 - 8 (1 bit)
TEMD : Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 9 - 9 (1 bit)
ASE : Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 10 - 10 (1 bit)
BSE : Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 11 - 11 (1 bit)
This register is used to control the concerned channel.
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : channel enable
bits : 0 - 0 (1 bit)
access : read-write
TEIE : Transfer error interrupt enable This bit is set and cleared by software.
bits : 1 - 1 (1 bit)
access : read-write
CTCIE : Channel Transfer Complete interrupt enable This bit is set and cleared by software.
bits : 2 - 2 (1 bit)
access : read-write
BRTIE : Block Repeat transfer interrupt enable This bit is set and cleared by software.
bits : 3 - 3 (1 bit)
access : read-write
BTIE : Block Transfer interrupt enable This bit is set and cleared by software.
bits : 4 - 4 (1 bit)
access : read-write
TCIE : buffer Transfer Complete interrupt enable This bit is set and cleared by software.
bits : 5 - 5 (1 bit)
access : read-write
PL : Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0.
bits : 6 - 7 (2 bit)
access : read-write
BEX : byte Endianness exchange
bits : 12 - 12 (1 bit)
access : read-write
HEX : Half word Endianes exchange
bits : 13 - 13 (1 bit)
access : read-write
WEX : Word Endianness exchange
bits : 14 - 14 (1 bit)
access : read-write
SWRQ : SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access).
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel.
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
bits : 0 - 1 (2 bit)
DINC : Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden.
bits : 2 - 3 (2 bit)
SSIZE : Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS < SSIZE and SINC ≠ 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1).
bits : 4 - 5 (2 bit)
DSIZE : Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS < DSIZE and DINC ≠ 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1).
bits : 6 - 7 (2 bit)
SINCOS : source increment offset size
bits : 8 - 9 (2 bit)
DINCOS : Destination increment offset
bits : 10 - 11 (2 bit)
SBURST : source burst transfer configuration
bits : 12 - 14 (3 bit)
DBURST : Destination burst transfer configuration
bits : 15 - 17 (3 bit)
TLEN : buffer transfer lengh
bits : 18 - 24 (7 bit)
PKE : PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0
bits : 25 - 25 (1 bit)
PAM : Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0
bits : 26 - 27 (2 bit)
TRGM : Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0.
bits : 28 - 29 (2 bit)
SWRM : SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0.
bits : 30 - 30 (1 bit)
BWM : Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable.
bits : 31 - 31 (1 bit)
MDMA Channel x block number of data register
address_offset : 0x1D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : block number of data to transfer
bits : 0 - 16 (17 bit)
BRSUM : Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0.
bits : 18 - 18 (1 bit)
BRDUM : Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0.
bits : 19 - 19 (1 bit)
BRC : Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0
bits : 20 - 31 (12 bit)
MDMA channel x source address register
address_offset : 0x1D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : source adr base
bits : 0 - 31 (32 bit)
MDMA channel x destination address register
address_offset : 0x1DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : Destination adr base
bits : 0 - 31 (32 bit)
MDMA channel x Block Repeat address Update register
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : source adresse update value
bits : 0 - 15 (16 bit)
DUV : destination address update
bits : 16 - 31 (16 bit)
MDMA channel x Link Address register
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : Link address register
bits : 0 - 31 (32 bit)
MDMA channel x Trigger and Bus selection Register
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : Trigger selection
bits : 0 - 5 (6 bit)
SBUS : Source BUS select This bit is protected and can be written only if EN is 0.
bits : 16 - 16 (1 bit)
DBUS : Destination BUS slect This bit is protected and can be written only if EN is 0.
bits : 17 - 17 (1 bit)
MDMA channel x Mask address register
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : Mask address
bits : 0 - 31 (32 bit)
MDMA channel x Mask Data register
address_offset : 0x1F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : Mask data
bits : 0 - 31 (32 bit)
MDMA channel x interrupt/status register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF7 : Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
bits : 0 - 0 (1 bit)
CTCIF7 : Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0.
bits : 1 - 1 (1 bit)
BRTIF7 : Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
bits : 2 - 2 (1 bit)
BTIF7 : Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
bits : 3 - 3 (1 bit)
TCIF7 : channel x buffer transfer complete
bits : 4 - 4 (1 bit)
CRQA7 : channel x request active flag
bits : 16 - 16 (1 bit)
MDMA channel x interrupt flag clear register
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CTEIF7 : Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register
bits : 0 - 0 (1 bit)
CCTCIF7 : Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register
bits : 1 - 1 (1 bit)
CBRTIF7 : Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register
bits : 2 - 2 (1 bit)
CBTIF7 : Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register
bits : 3 - 3 (1 bit)
CLTCIF7 : CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register
bits : 4 - 4 (1 bit)
MDMA Channel x error status register
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error.
bits : 0 - 6 (7 bit)
TED : Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error.
bits : 7 - 7 (1 bit)
TELD : Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 8 - 8 (1 bit)
TEMD : Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 9 - 9 (1 bit)
ASE : Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 10 - 10 (1 bit)
BSE : Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 11 - 11 (1 bit)
This register is used to control the concerned channel.
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : channel enable
bits : 0 - 0 (1 bit)
access : read-write
TEIE : Transfer error interrupt enable This bit is set and cleared by software.
bits : 1 - 1 (1 bit)
access : read-write
CTCIE : Channel Transfer Complete interrupt enable This bit is set and cleared by software.
bits : 2 - 2 (1 bit)
access : read-write
BRTIE : Block Repeat transfer interrupt enable This bit is set and cleared by software.
bits : 3 - 3 (1 bit)
access : read-write
BTIE : Block Transfer interrupt enable This bit is set and cleared by software.
bits : 4 - 4 (1 bit)
access : read-write
TCIE : buffer Transfer Complete interrupt enable This bit is set and cleared by software.
bits : 5 - 5 (1 bit)
access : read-write
PL : Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0.
bits : 6 - 7 (2 bit)
access : read-write
BEX : byte Endianness exchange
bits : 12 - 12 (1 bit)
access : read-write
HEX : Half word Endianes exchange
bits : 13 - 13 (1 bit)
access : read-write
WEX : Word Endianness exchange
bits : 14 - 14 (1 bit)
access : read-write
SWRQ : SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access).
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel.
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
bits : 0 - 1 (2 bit)
DINC : Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden.
bits : 2 - 3 (2 bit)
SSIZE : Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS < SSIZE and SINC ≠ 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1).
bits : 4 - 5 (2 bit)
DSIZE : Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS < DSIZE and DINC ≠ 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1).
bits : 6 - 7 (2 bit)
SINCOS : source increment offset size
bits : 8 - 9 (2 bit)
DINCOS : Destination increment offset
bits : 10 - 11 (2 bit)
SBURST : source burst transfer configuration
bits : 12 - 14 (3 bit)
DBURST : Destination burst transfer configuration
bits : 15 - 17 (3 bit)
TLEN : buffer transfer lengh
bits : 18 - 24 (7 bit)
PKE : PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0
bits : 25 - 25 (1 bit)
PAM : Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0
bits : 26 - 27 (2 bit)
TRGM : Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0.
bits : 28 - 29 (2 bit)
SWRM : SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0.
bits : 30 - 30 (1 bit)
BWM : Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable.
bits : 31 - 31 (1 bit)
MDMA Channel x block number of data register
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : block number of data to transfer
bits : 0 - 16 (17 bit)
BRSUM : Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0.
bits : 18 - 18 (1 bit)
BRDUM : Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0.
bits : 19 - 19 (1 bit)
BRC : Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0.
bits : 20 - 31 (12 bit)
MDMA channel x source address register
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : source adr base
bits : 0 - 31 (32 bit)
MDMA channel x destination address register
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : Destination adr base
bits : 0 - 31 (32 bit)
MDMA channel x Block Repeat address Update register
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : source adresse update value
bits : 0 - 15 (16 bit)
DUV : destination address update
bits : 16 - 31 (16 bit)
MDMA channel x Link Address register
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : Link address register
bits : 0 - 31 (32 bit)
MDMA channel x Trigger and Bus selection Register
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : Trigger selection
bits : 0 - 5 (6 bit)
SBUS : Source BUS select This bit is protected and can be written only if EN is 0.
bits : 16 - 16 (1 bit)
DBUS : Destination BUS slect This bit is protected and can be written only if EN is 0.
bits : 17 - 17 (1 bit)
MDMA channel x Mask address register
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : Mask address
bits : 0 - 31 (32 bit)
MDMA channel x Mask Data register
address_offset : 0x234 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : Mask data
bits : 0 - 31 (32 bit)
MDMA channel x interrupt/status register
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF8 : Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
bits : 0 - 0 (1 bit)
CTCIF8 : Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0.
bits : 1 - 1 (1 bit)
BRTIF8 : Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
bits : 2 - 2 (1 bit)
BTIF8 : Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
bits : 3 - 3 (1 bit)
TCIF8 : channel x buffer transfer complete
bits : 4 - 4 (1 bit)
CRQA8 : channel x request active flag
bits : 16 - 16 (1 bit)
MDMA channel x interrupt flag clear register
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CTEIF8 : Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register
bits : 0 - 0 (1 bit)
CCTCIF8 : Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register
bits : 1 - 1 (1 bit)
CBRTIF8 : Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register
bits : 2 - 2 (1 bit)
CBTIF8 : Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register
bits : 3 - 3 (1 bit)
CLTCIF8 : CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register
bits : 4 - 4 (1 bit)
MDMA Channel x error status register
address_offset : 0x248 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error.
bits : 0 - 6 (7 bit)
TED : Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error.
bits : 7 - 7 (1 bit)
TELD : Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 8 - 8 (1 bit)
TEMD : Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 9 - 9 (1 bit)
ASE : Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 10 - 10 (1 bit)
BSE : Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 11 - 11 (1 bit)
This register is used to control the concerned channel.
address_offset : 0x24C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : channel enable
bits : 0 - 0 (1 bit)
access : read-write
TEIE : Transfer error interrupt enable This bit is set and cleared by software.
bits : 1 - 1 (1 bit)
access : read-write
CTCIE : Channel Transfer Complete interrupt enable This bit is set and cleared by software.
bits : 2 - 2 (1 bit)
access : read-write
BRTIE : Block Repeat transfer interrupt enable This bit is set and cleared by software.
bits : 3 - 3 (1 bit)
access : read-write
BTIE : Block Transfer interrupt enable This bit is set and cleared by software.
bits : 4 - 4 (1 bit)
access : read-write
TCIE : buffer Transfer Complete interrupt enable This bit is set and cleared by software.
bits : 5 - 5 (1 bit)
access : read-write
PL : Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0.
bits : 6 - 7 (2 bit)
access : read-write
BEX : byte Endianness exchange
bits : 12 - 12 (1 bit)
access : read-write
HEX : Half word Endianes exchange
bits : 13 - 13 (1 bit)
access : read-write
WEX : Word Endianness exchange
bits : 14 - 14 (1 bit)
access : read-write
SWRQ : SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access).
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel.
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
bits : 0 - 1 (2 bit)
DINC : Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden.
bits : 2 - 3 (2 bit)
SSIZE : Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS < SSIZE and SINC ≠ 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1).
bits : 4 - 5 (2 bit)
DSIZE : Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS < DSIZE and DINC ≠ 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1).
bits : 6 - 7 (2 bit)
SINCOS : source increment offset size
bits : 8 - 9 (2 bit)
DINCOS : Destination increment offset
bits : 10 - 11 (2 bit)
SBURST : source burst transfer configuration
bits : 12 - 14 (3 bit)
DBURST : Destination burst transfer configuration
bits : 15 - 17 (3 bit)
TLEN : buffer transfer lengh
bits : 18 - 24 (7 bit)
PKE : PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0
bits : 25 - 25 (1 bit)
PAM : Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0
bits : 26 - 27 (2 bit)
TRGM : Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0.
bits : 28 - 29 (2 bit)
SWRM : SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0.
bits : 30 - 30 (1 bit)
BWM : Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable.
bits : 31 - 31 (1 bit)
MDMA Channel x block number of data register
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : block number of data to transfer
bits : 0 - 16 (17 bit)
BRSUM : Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0.
bits : 18 - 18 (1 bit)
BRDUM : Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0.
bits : 19 - 19 (1 bit)
BRC : Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0.
bits : 20 - 31 (12 bit)
MDMA channel x source address register
address_offset : 0x258 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : source adr base
bits : 0 - 31 (32 bit)
MDMA channel x destination address register
address_offset : 0x25C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : Destination adr base
bits : 0 - 31 (32 bit)
MDMA channel x Block Repeat address Update register
address_offset : 0x260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : source adresse update value
bits : 0 - 15 (16 bit)
DUV : destination address update
bits : 16 - 31 (16 bit)
MDMA channel x Link Address register
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : Link address register
bits : 0 - 31 (32 bit)
MDMA channel x Trigger and Bus selection Register
address_offset : 0x268 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : Trigger selection
bits : 0 - 5 (6 bit)
SBUS : Source BUS select This bit is protected and can be written only if EN is 0.
bits : 16 - 16 (1 bit)
DBUS : Destination BUS slect This bit is protected and can be written only if EN is 0.
bits : 17 - 17 (1 bit)
MDMA channel x Mask address register
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : Mask address
bits : 0 - 31 (32 bit)
MDMA channel x Mask Data register
address_offset : 0x274 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : Mask data
bits : 0 - 31 (32 bit)
MDMA channel x interrupt/status register
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF9 : Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
bits : 0 - 0 (1 bit)
CTCIF9 : Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0.
bits : 1 - 1 (1 bit)
BRTIF9 : Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
bits : 2 - 2 (1 bit)
BTIF9 : Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
bits : 3 - 3 (1 bit)
TCIF9 : channel x buffer transfer complete
bits : 4 - 4 (1 bit)
CRQA9 : channel x request active flag
bits : 16 - 16 (1 bit)
MDMA channel x interrupt flag clear register
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CTEIF9 : Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register
bits : 0 - 0 (1 bit)
CCTCIF9 : Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register
bits : 1 - 1 (1 bit)
CBRTIF9 : Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register
bits : 2 - 2 (1 bit)
CBTIF9 : Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register
bits : 3 - 3 (1 bit)
CLTCIF9 : CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register
bits : 4 - 4 (1 bit)
MDMA Channel x error status register
address_offset : 0x288 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error.
bits : 0 - 6 (7 bit)
TED : Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error.
bits : 7 - 7 (1 bit)
TELD : Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 8 - 8 (1 bit)
TEMD : Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 9 - 9 (1 bit)
ASE : Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 10 - 10 (1 bit)
BSE : Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 11 - 11 (1 bit)
This register is used to control the concerned channel.
address_offset : 0x28C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : channel enable
bits : 0 - 0 (1 bit)
access : read-write
TEIE : Transfer error interrupt enable This bit is set and cleared by software.
bits : 1 - 1 (1 bit)
access : read-write
CTCIE : Channel Transfer Complete interrupt enable This bit is set and cleared by software.
bits : 2 - 2 (1 bit)
access : read-write
BRTIE : Block Repeat transfer interrupt enable This bit is set and cleared by software.
bits : 3 - 3 (1 bit)
access : read-write
BTIE : Block Transfer interrupt enable This bit is set and cleared by software.
bits : 4 - 4 (1 bit)
access : read-write
TCIE : buffer Transfer Complete interrupt enable This bit is set and cleared by software.
bits : 5 - 5 (1 bit)
access : read-write
PL : Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0.
bits : 6 - 7 (2 bit)
access : read-write
BEX : byte Endianness exchange
bits : 12 - 12 (1 bit)
access : read-write
HEX : Half word Endianes exchange
bits : 13 - 13 (1 bit)
access : read-write
WEX : Word Endianness exchange
bits : 14 - 14 (1 bit)
access : read-write
SWRQ : SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access).
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel.
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
bits : 0 - 1 (2 bit)
DINC : Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden.
bits : 2 - 3 (2 bit)
SSIZE : Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS < SSIZE and SINC ≠ 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1).
bits : 4 - 5 (2 bit)
DSIZE : Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS < DSIZE and DINC ≠ 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1).
bits : 6 - 7 (2 bit)
SINCOS : source increment offset size
bits : 8 - 9 (2 bit)
DINCOS : Destination increment offset
bits : 10 - 11 (2 bit)
SBURST : source burst transfer configuration
bits : 12 - 14 (3 bit)
DBURST : Destination burst transfer configuration
bits : 15 - 17 (3 bit)
TLEN : buffer transfer lengh
bits : 18 - 24 (7 bit)
PKE : PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0
bits : 25 - 25 (1 bit)
PAM : Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0
bits : 26 - 27 (2 bit)
TRGM : Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0.
bits : 28 - 29 (2 bit)
SWRM : SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0.
bits : 30 - 30 (1 bit)
BWM : Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable.
bits : 31 - 31 (1 bit)
MDMA Channel x block number of data register
address_offset : 0x294 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : block number of data to transfer
bits : 0 - 16 (17 bit)
BRSUM : Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0.
bits : 18 - 18 (1 bit)
BRDUM : Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0.
bits : 19 - 19 (1 bit)
BRC : Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0.
bits : 20 - 31 (12 bit)
MDMA channel x source address register
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : source adr base
bits : 0 - 31 (32 bit)
MDMA channel x destination address register
address_offset : 0x29C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : Destination adr base
bits : 0 - 31 (32 bit)
MDMA channel x Block Repeat address Update register
address_offset : 0x2A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : source adresse update value
bits : 0 - 15 (16 bit)
DUV : destination address update
bits : 16 - 31 (16 bit)
MDMA channel x Link Address register
address_offset : 0x2A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : Link address register
bits : 0 - 31 (32 bit)
MDMA channel x Trigger and Bus selection Register
address_offset : 0x2A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : Trigger selection
bits : 0 - 5 (6 bit)
SBUS : Source BUS select This bit is protected and can be written only if EN is 0.
bits : 16 - 16 (1 bit)
DBUS : Destination BUS slect This bit is protected and can be written only if EN is 0.
bits : 17 - 17 (1 bit)
MDMA channel x Mask address register
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : Mask address
bits : 0 - 31 (32 bit)
MDMA channel x Mask Data register
address_offset : 0x2B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : Mask data
bits : 0 - 31 (32 bit)
MDMA channel x interrupt/status register
address_offset : 0x2C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF10 : Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
bits : 0 - 0 (1 bit)
CTCIF10 : Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0.
bits : 1 - 1 (1 bit)
BRTIF10 : Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
bits : 2 - 2 (1 bit)
BTIF10 : Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
bits : 3 - 3 (1 bit)
TCIF10 : channel x buffer transfer complete
bits : 4 - 4 (1 bit)
CRQA10 : channel x request active flag
bits : 16 - 16 (1 bit)
MDMA channel x interrupt flag clear register
address_offset : 0x2C4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CTEIF10 : Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register
bits : 0 - 0 (1 bit)
CCTCIF10 : Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register
bits : 1 - 1 (1 bit)
CBRTIF10 : Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register
bits : 2 - 2 (1 bit)
CBTIF10 : Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register
bits : 3 - 3 (1 bit)
CLTCIF10 : CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register
bits : 4 - 4 (1 bit)
MDMA Channel x error status register
address_offset : 0x2C8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error.
bits : 0 - 6 (7 bit)
TED : Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error.
bits : 7 - 7 (1 bit)
TELD : Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 8 - 8 (1 bit)
TEMD : Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 9 - 9 (1 bit)
ASE : Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 10 - 10 (1 bit)
BSE : Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 11 - 11 (1 bit)
This register is used to control the concerned channel.
address_offset : 0x2CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : channel enable
bits : 0 - 0 (1 bit)
access : read-write
TEIE : Transfer error interrupt enable This bit is set and cleared by software.
bits : 1 - 1 (1 bit)
access : read-write
CTCIE : Channel Transfer Complete interrupt enable This bit is set and cleared by software.
bits : 2 - 2 (1 bit)
access : read-write
BRTIE : Block Repeat transfer interrupt enable This bit is set and cleared by software.
bits : 3 - 3 (1 bit)
access : read-write
BTIE : Block Transfer interrupt enable This bit is set and cleared by software.
bits : 4 - 4 (1 bit)
access : read-write
TCIE : buffer Transfer Complete interrupt enable This bit is set and cleared by software.
bits : 5 - 5 (1 bit)
access : read-write
PL : Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0.
bits : 6 - 7 (2 bit)
access : read-write
BEX : byte Endianness exchange
bits : 12 - 12 (1 bit)
access : read-write
HEX : Half word Endianes exchange
bits : 13 - 13 (1 bit)
access : read-write
WEX : Word Endianness exchange
bits : 14 - 14 (1 bit)
access : read-write
SWRQ : SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access).
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel.
address_offset : 0x2D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
bits : 0 - 1 (2 bit)
DINC : Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden.
bits : 2 - 3 (2 bit)
SSIZE : Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS < SSIZE and SINC ≠ 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1).
bits : 4 - 5 (2 bit)
DSIZE : Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS < DSIZE and DINC ≠ 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1).
bits : 6 - 7 (2 bit)
SINCOS : source increment offset size
bits : 8 - 9 (2 bit)
DINCOS : Destination increment offset
bits : 10 - 11 (2 bit)
SBURST : source burst transfer configuration
bits : 12 - 14 (3 bit)
DBURST : Destination burst transfer configuration
bits : 15 - 17 (3 bit)
TLEN : buffer transfer lengh
bits : 18 - 24 (7 bit)
PKE : PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0
bits : 25 - 25 (1 bit)
PAM : Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0
bits : 26 - 27 (2 bit)
TRGM : Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0.
bits : 28 - 29 (2 bit)
SWRM : SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0.
bits : 30 - 30 (1 bit)
BWM : Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable.
bits : 31 - 31 (1 bit)
MDMA Channel x block number of data register
address_offset : 0x2D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : block number of data to transfer
bits : 0 - 16 (17 bit)
BRSUM : Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0.
bits : 18 - 18 (1 bit)
BRDUM : Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0.
bits : 19 - 19 (1 bit)
BRC : Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0.
bits : 20 - 31 (12 bit)
MDMA channel x source address register
address_offset : 0x2D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : source adr base
bits : 0 - 31 (32 bit)
MDMA channel x destination address register
address_offset : 0x2DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : Destination adr base
bits : 0 - 31 (32 bit)
MDMA channel x Block Repeat address Update register
address_offset : 0x2E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : source adresse update value
bits : 0 - 15 (16 bit)
DUV : destination address update
bits : 16 - 31 (16 bit)
MDMA channel x Link Address register
address_offset : 0x2E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : Link address register
bits : 0 - 31 (32 bit)
MDMA channel x Trigger and Bus selection Register
address_offset : 0x2E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : Trigger selection
bits : 0 - 5 (6 bit)
SBUS : Source BUS select This bit is protected and can be written only if EN is 0.
bits : 16 - 16 (1 bit)
DBUS : Destination BUS slect This bit is protected and can be written only if EN is 0.
bits : 17 - 17 (1 bit)
MDMA channel x Mask address register
address_offset : 0x2F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : Mask address
bits : 0 - 31 (32 bit)
MDMA channel x Mask Data register
address_offset : 0x2F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : Mask data
bits : 0 - 31 (32 bit)
MDMA channel x interrupt/status register
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF11 : Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
bits : 0 - 0 (1 bit)
CTCIF11 : Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0.
bits : 1 - 1 (1 bit)
BRTIF11 : Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
bits : 2 - 2 (1 bit)
BTIF11 : Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
bits : 3 - 3 (1 bit)
TCIF11 : channel x buffer transfer complete
bits : 4 - 4 (1 bit)
CRQA11 : channel x request active flag
bits : 16 - 16 (1 bit)
MDMA channel x interrupt flag clear register
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CTEIF11 : Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register
bits : 0 - 0 (1 bit)
CCTCIF11 : Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register
bits : 1 - 1 (1 bit)
CBRTIF11 : Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register
bits : 2 - 2 (1 bit)
CBTIF11 : Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register
bits : 3 - 3 (1 bit)
CLTCIF11 : CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register
bits : 4 - 4 (1 bit)
MDMA Channel x error status register
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error.
bits : 0 - 6 (7 bit)
TED : Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error.
bits : 7 - 7 (1 bit)
TELD : Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 8 - 8 (1 bit)
TEMD : Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 9 - 9 (1 bit)
ASE : Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 10 - 10 (1 bit)
BSE : Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 11 - 11 (1 bit)
This register is used to control the concerned channel.
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : channel enable
bits : 0 - 0 (1 bit)
access : read-write
TEIE : Transfer error interrupt enable This bit is set and cleared by software.
bits : 1 - 1 (1 bit)
access : read-write
CTCIE : Channel Transfer Complete interrupt enable This bit is set and cleared by software.
bits : 2 - 2 (1 bit)
access : read-write
BRTIE : Block Repeat transfer interrupt enable This bit is set and cleared by software.
bits : 3 - 3 (1 bit)
access : read-write
BTIE : Block Transfer interrupt enable This bit is set and cleared by software.
bits : 4 - 4 (1 bit)
access : read-write
TCIE : buffer Transfer Complete interrupt enable This bit is set and cleared by software.
bits : 5 - 5 (1 bit)
access : read-write
PL : Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0.
bits : 6 - 7 (2 bit)
access : read-write
BEX : byte Endianness exchange
bits : 12 - 12 (1 bit)
access : read-write
HEX : Half word Endianes exchange
bits : 13 - 13 (1 bit)
access : read-write
WEX : Word Endianness exchange
bits : 14 - 14 (1 bit)
access : read-write
SWRQ : SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access).
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel.
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
bits : 0 - 1 (2 bit)
DINC : Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden.
bits : 2 - 3 (2 bit)
SSIZE : Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS < SSIZE and SINC ≠ 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1).
bits : 4 - 5 (2 bit)
DSIZE : Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS < DSIZE and DINC ≠ 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1).
bits : 6 - 7 (2 bit)
SINCOS : source increment offset size
bits : 8 - 9 (2 bit)
DINCOS : Destination increment offset
bits : 10 - 11 (2 bit)
SBURST : source burst transfer configuration
bits : 12 - 14 (3 bit)
DBURST : Destination burst transfer configuration
bits : 15 - 17 (3 bit)
TLEN : buffer transfer lengh
bits : 18 - 24 (7 bit)
PKE : PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0
bits : 25 - 25 (1 bit)
PAM : Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0
bits : 26 - 27 (2 bit)
TRGM : Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0.
bits : 28 - 29 (2 bit)
SWRM : SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0.
bits : 30 - 30 (1 bit)
BWM : Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable.
bits : 31 - 31 (1 bit)
MDMA Channel x block number of data register
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : block number of data to transfer
bits : 0 - 16 (17 bit)
BRSUM : Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0.
bits : 18 - 18 (1 bit)
BRDUM : Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0.
bits : 19 - 19 (1 bit)
BRC : Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0.
bits : 20 - 31 (12 bit)
MDMA channel x source address register
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : source adr base
bits : 0 - 31 (32 bit)
MDMA channel x destination address register
address_offset : 0x31C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : Destination adr base
bits : 0 - 31 (32 bit)
MDMA channel x Block Repeat address Update register
address_offset : 0x320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : source adresse update value
bits : 0 - 15 (16 bit)
DUV : destination address update
bits : 16 - 31 (16 bit)
MDMA channel x Link Address register
address_offset : 0x324 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : Link address register
bits : 0 - 31 (32 bit)
MDMA channel x Trigger and Bus selection Register
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : Trigger selection
bits : 0 - 5 (6 bit)
SBUS : Source BUS select This bit is protected and can be written only if EN is 0.
bits : 16 - 16 (1 bit)
DBUS : Destination BUS slect This bit is protected and can be written only if EN is 0.
bits : 17 - 17 (1 bit)
MDMA channel x Mask address register
address_offset : 0x330 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : Mask address
bits : 0 - 31 (32 bit)
MDMA channel x Mask Data register
address_offset : 0x334 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : Mask data
bits : 0 - 31 (32 bit)
MDMA channel x interrupt/status register
address_offset : 0x340 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF12 : Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
bits : 0 - 0 (1 bit)
CTCIF12 : Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0.
bits : 1 - 1 (1 bit)
BRTIF12 : Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
bits : 2 - 2 (1 bit)
BTIF12 : Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
bits : 3 - 3 (1 bit)
TCIF12 : channel x buffer transfer complete
bits : 4 - 4 (1 bit)
CRQA12 : channel x request active flag
bits : 16 - 16 (1 bit)
MDMA channel x interrupt flag clear register
address_offset : 0x344 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CTEIF12 : Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register
bits : 0 - 0 (1 bit)
CCTCIF12 : Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register
bits : 1 - 1 (1 bit)
CBRTIF12 : Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register
bits : 2 - 2 (1 bit)
CBTIF12 : Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register
bits : 3 - 3 (1 bit)
CLTCIF12 : CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register
bits : 4 - 4 (1 bit)
MDMA Channel x error status register
address_offset : 0x348 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error.
bits : 0 - 6 (7 bit)
TED : Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error.
bits : 7 - 7 (1 bit)
TELD : Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 8 - 8 (1 bit)
TEMD : Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 9 - 9 (1 bit)
ASE : Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 10 - 10 (1 bit)
BSE : Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 11 - 11 (1 bit)
This register is used to control the concerned channel.
address_offset : 0x34C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : channel enable
bits : 0 - 0 (1 bit)
access : read-write
TEIE : Transfer error interrupt enable This bit is set and cleared by software.
bits : 1 - 1 (1 bit)
access : read-write
CTCIE : Channel Transfer Complete interrupt enable This bit is set and cleared by software.
bits : 2 - 2 (1 bit)
access : read-write
BRTIE : Block Repeat transfer interrupt enable This bit is set and cleared by software.
bits : 3 - 3 (1 bit)
access : read-write
BTIE : Block Transfer interrupt enable This bit is set and cleared by software.
bits : 4 - 4 (1 bit)
access : read-write
TCIE : buffer Transfer Complete interrupt enable This bit is set and cleared by software.
bits : 5 - 5 (1 bit)
access : read-write
PL : Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0.
bits : 6 - 7 (2 bit)
access : read-write
BEX : byte Endianness exchange
bits : 12 - 12 (1 bit)
access : read-write
HEX : Half word Endianes exchange
bits : 13 - 13 (1 bit)
access : read-write
WEX : Word Endianness exchange
bits : 14 - 14 (1 bit)
access : read-write
SWRQ : SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access).
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel.
address_offset : 0x350 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
bits : 0 - 1 (2 bit)
DINC : Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden.
bits : 2 - 3 (2 bit)
SSIZE : Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS < SSIZE and SINC ≠ 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1).
bits : 4 - 5 (2 bit)
DSIZE : Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS < DSIZE and DINC ≠ 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1).
bits : 6 - 7 (2 bit)
SINCOS : source increment offset size
bits : 8 - 9 (2 bit)
DINCOS : Destination increment offset
bits : 10 - 11 (2 bit)
SBURST : source burst transfer configuration
bits : 12 - 14 (3 bit)
DBURST : Destination burst transfer configuration
bits : 15 - 17 (3 bit)
TLEN : buffer transfer lengh
bits : 18 - 24 (7 bit)
PKE : PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0
bits : 25 - 25 (1 bit)
PAM : Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0
bits : 26 - 27 (2 bit)
TRGM : Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0.
bits : 28 - 29 (2 bit)
SWRM : SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0.
bits : 30 - 30 (1 bit)
BWM : Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable.
bits : 31 - 31 (1 bit)
MDMA Channel x block number of data register
address_offset : 0x354 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : block number of data to transfer
bits : 0 - 16 (17 bit)
BRSUM : Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0.
bits : 18 - 18 (1 bit)
BRDUM : Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0.
bits : 19 - 19 (1 bit)
BRC : Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0.
bits : 20 - 31 (12 bit)
MDMA channel x source address register
address_offset : 0x358 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : source adr base
bits : 0 - 31 (32 bit)
MDMA channel x destination address register
address_offset : 0x35C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : Destination adr base
bits : 0 - 31 (32 bit)
MDMA channel x Block Repeat address Update register
address_offset : 0x360 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : source adresse update value
bits : 0 - 15 (16 bit)
DUV : destination address update
bits : 16 - 31 (16 bit)
MDMA channel x Link Address register
address_offset : 0x364 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : Link address register
bits : 0 - 31 (32 bit)
MDMA channel x Trigger and Bus selection Register
address_offset : 0x368 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : Trigger selection
bits : 0 - 5 (6 bit)
SBUS : Source BUS select This bit is protected and can be written only if EN is 0.
bits : 16 - 16 (1 bit)
DBUS : Destination BUS slect This bit is protected and can be written only if EN is 0.
bits : 17 - 17 (1 bit)
MDMA channel x Mask address register
address_offset : 0x370 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : Mask address
bits : 0 - 31 (32 bit)
MDMA channel x Mask Data register
address_offset : 0x374 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : Mask data
bits : 0 - 31 (32 bit)
MDMA channel x interrupt/status register
address_offset : 0x380 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF13 : Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
bits : 0 - 0 (1 bit)
CTCIF13 : Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0.
bits : 1 - 1 (1 bit)
BRTIF13 : Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
bits : 2 - 2 (1 bit)
BTIF13 : Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
bits : 3 - 3 (1 bit)
TCIF13 : channel x buffer transfer complete
bits : 4 - 4 (1 bit)
CRQA13 : channel x request active flag
bits : 16 - 16 (1 bit)
MDMA channel x interrupt flag clear register
address_offset : 0x384 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CTEIF13 : Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register
bits : 0 - 0 (1 bit)
CCTCIF13 : Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register
bits : 1 - 1 (1 bit)
CBRTIF13 : Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register
bits : 2 - 2 (1 bit)
CBTIF13 : Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register
bits : 3 - 3 (1 bit)
CLTCIF13 : CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register
bits : 4 - 4 (1 bit)
MDMA Channel x error status register
address_offset : 0x388 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error.
bits : 0 - 6 (7 bit)
TED : Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error.
bits : 7 - 7 (1 bit)
TELD : Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 8 - 8 (1 bit)
TEMD : Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 9 - 9 (1 bit)
ASE : Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 10 - 10 (1 bit)
BSE : Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 11 - 11 (1 bit)
This register is used to control the concerned channel.
address_offset : 0x38C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : channel enable
bits : 0 - 0 (1 bit)
access : read-write
TEIE : Transfer error interrupt enable This bit is set and cleared by software.
bits : 1 - 1 (1 bit)
access : read-write
CTCIE : Channel Transfer Complete interrupt enable This bit is set and cleared by software.
bits : 2 - 2 (1 bit)
access : read-write
BRTIE : Block Repeat transfer interrupt enable This bit is set and cleared by software.
bits : 3 - 3 (1 bit)
access : read-write
BTIE : Block Transfer interrupt enable This bit is set and cleared by software.
bits : 4 - 4 (1 bit)
access : read-write
TCIE : buffer Transfer Complete interrupt enable This bit is set and cleared by software.
bits : 5 - 5 (1 bit)
access : read-write
PL : Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0.
bits : 6 - 7 (2 bit)
access : read-write
BEX : byte Endianness exchange
bits : 12 - 12 (1 bit)
access : read-write
HEX : Half word Endianes exchange
bits : 13 - 13 (1 bit)
access : read-write
WEX : Word Endianness exchange
bits : 14 - 14 (1 bit)
access : read-write
SWRQ : SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access).
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel.
address_offset : 0x390 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
bits : 0 - 1 (2 bit)
DINC : Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden.
bits : 2 - 3 (2 bit)
SSIZE : Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS < SSIZE and SINC ≠ 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1).
bits : 4 - 5 (2 bit)
DSIZE : Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS < DSIZE and DINC ≠ 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1).
bits : 6 - 7 (2 bit)
SINCOS : source increment offset size
bits : 8 - 9 (2 bit)
DINCOS : Destination increment offset
bits : 10 - 11 (2 bit)
SBURST : source burst transfer configuration
bits : 12 - 14 (3 bit)
DBURST : Destination burst transfer configuration
bits : 15 - 17 (3 bit)
TLEN : buffer transfer lengh
bits : 18 - 24 (7 bit)
PKE : PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0
bits : 25 - 25 (1 bit)
PAM : Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0
bits : 26 - 27 (2 bit)
TRGM : Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0.
bits : 28 - 29 (2 bit)
SWRM : SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0.
bits : 30 - 30 (1 bit)
BWM : Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable.
bits : 31 - 31 (1 bit)
MDMA Channel x block number of data register
address_offset : 0x394 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : block number of data to transfer
bits : 0 - 16 (17 bit)
BRSUM : Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0.
bits : 18 - 18 (1 bit)
BRDUM : Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0.
bits : 19 - 19 (1 bit)
BRC : Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0.
bits : 20 - 31 (12 bit)
MDMA channel x source address register
address_offset : 0x398 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : source adr base
bits : 0 - 31 (32 bit)
MDMA channel x destination address register
address_offset : 0x39C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : Destination adr base
bits : 0 - 31 (32 bit)
MDMA channel x Block Repeat address Update register
address_offset : 0x3A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : source adresse update value
bits : 0 - 15 (16 bit)
DUV : destination address update
bits : 16 - 31 (16 bit)
MDMA channel x Link Address register
address_offset : 0x3A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : Link address register
bits : 0 - 31 (32 bit)
MDMA channel x Trigger and Bus selection Register
address_offset : 0x3A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : Trigger selection
bits : 0 - 5 (6 bit)
SBUS : Source BUS select This bit is protected and can be written only if EN is 0.
bits : 16 - 16 (1 bit)
DBUS : Destination BUS slect This bit is protected and can be written only if EN is 0.
bits : 17 - 17 (1 bit)
MDMA channel x Mask address register
address_offset : 0x3B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : Mask address
bits : 0 - 31 (32 bit)
MDMA channel x Mask Data register
address_offset : 0x3B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : Mask data
bits : 0 - 31 (32 bit)
MDMA channel x interrupt/status register
address_offset : 0x3C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF14 : Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
bits : 0 - 0 (1 bit)
CTCIF14 : Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0.
bits : 1 - 1 (1 bit)
BRTIF14 : Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
bits : 2 - 2 (1 bit)
BTIF14 : Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
bits : 3 - 3 (1 bit)
TCIF14 : channel x buffer transfer complete
bits : 4 - 4 (1 bit)
CRQA14 : channel x request active flag
bits : 16 - 16 (1 bit)
MDMA channel x interrupt flag clear register
address_offset : 0x3C4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CTEIF14 : Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register
bits : 0 - 0 (1 bit)
CCTCIF14 : Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register
bits : 1 - 1 (1 bit)
CBRTIF14 : Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register
bits : 2 - 2 (1 bit)
CBTIF14 : Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register
bits : 3 - 3 (1 bit)
CLTCIF14 : CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register
bits : 4 - 4 (1 bit)
MDMA Channel x error status register
address_offset : 0x3C8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error.
bits : 0 - 6 (7 bit)
TED : Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error.
bits : 7 - 7 (1 bit)
TELD : Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 8 - 8 (1 bit)
TEMD : Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 9 - 9 (1 bit)
ASE : Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 10 - 10 (1 bit)
BSE : Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 11 - 11 (1 bit)
This register is used to control the concerned channel.
address_offset : 0x3CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : channel enable
bits : 0 - 0 (1 bit)
access : read-write
TEIE : Transfer error interrupt enable This bit is set and cleared by software.
bits : 1 - 1 (1 bit)
access : read-write
CTCIE : Channel Transfer Complete interrupt enable This bit is set and cleared by software.
bits : 2 - 2 (1 bit)
access : read-write
BRTIE : Block Repeat transfer interrupt enable This bit is set and cleared by software.
bits : 3 - 3 (1 bit)
access : read-write
BTIE : Block Transfer interrupt enable This bit is set and cleared by software.
bits : 4 - 4 (1 bit)
access : read-write
TCIE : buffer Transfer Complete interrupt enable This bit is set and cleared by software.
bits : 5 - 5 (1 bit)
access : read-write
PL : Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0.
bits : 6 - 7 (2 bit)
access : read-write
BEX : byte Endianness exchange
bits : 12 - 12 (1 bit)
access : read-write
HEX : Half word Endianes exchange
bits : 13 - 13 (1 bit)
access : read-write
WEX : Word Endianness exchange
bits : 14 - 14 (1 bit)
access : read-write
SWRQ : SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access).
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel.
address_offset : 0x3D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
bits : 0 - 1 (2 bit)
DINC : Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden.
bits : 2 - 3 (2 bit)
SSIZE : Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS < SSIZE and SINC ≠ 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1).
bits : 4 - 5 (2 bit)
DSIZE : Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS < DSIZE and DINC ≠ 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1).
bits : 6 - 7 (2 bit)
SINCOS : source increment offset size
bits : 8 - 9 (2 bit)
DINCOS : Destination increment offset
bits : 10 - 11 (2 bit)
SBURST : source burst transfer configuration
bits : 12 - 14 (3 bit)
DBURST : Destination burst transfer configuration
bits : 15 - 17 (3 bit)
TLEN : buffer transfer lengh
bits : 18 - 24 (7 bit)
PKE : PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0
bits : 25 - 25 (1 bit)
PAM : Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0
bits : 26 - 27 (2 bit)
TRGM : Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0.
bits : 28 - 29 (2 bit)
SWRM : SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0.
bits : 30 - 30 (1 bit)
BWM : Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable.
bits : 31 - 31 (1 bit)
MDMA Channel x block number of data register
address_offset : 0x3D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : block number of data to transfer
bits : 0 - 16 (17 bit)
BRSUM : Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0.
bits : 18 - 18 (1 bit)
BRDUM : Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0.
bits : 19 - 19 (1 bit)
BRC : Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0.
bits : 20 - 31 (12 bit)
MDMA channel x source address register
address_offset : 0x3D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : source adr base
bits : 0 - 31 (32 bit)
MDMA channel x destination address register
address_offset : 0x3DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : Destination adr base
bits : 0 - 31 (32 bit)
MDMA channel x Block Repeat address Update register
address_offset : 0x3E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : source adresse update value
bits : 0 - 15 (16 bit)
DUV : destination address update
bits : 16 - 31 (16 bit)
MDMA channel x Link Address register
address_offset : 0x3E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : Link address register
bits : 0 - 31 (32 bit)
MDMA channel x Trigger and Bus selection Register
address_offset : 0x3E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : Trigger selection
bits : 0 - 5 (6 bit)
SBUS : Source BUS select This bit is protected and can be written only if EN is 0.
bits : 16 - 16 (1 bit)
DBUS : Destination BUS slect This bit is protected and can be written only if EN is 0.
bits : 17 - 17 (1 bit)
MDMA channel x Mask address register
address_offset : 0x3F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : Mask address
bits : 0 - 31 (32 bit)
MDMA channel x Mask Data register
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : Mask data
bits : 0 - 31 (32 bit)
MDMA channel x interrupt/status register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF0 : Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
bits : 0 - 0 (1 bit)
CTCIF0 : Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0.
bits : 1 - 1 (1 bit)
BRTIF0 : Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
bits : 2 - 2 (1 bit)
BTIF0 : Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
bits : 3 - 3 (1 bit)
TCIF0 : channel x buffer transfer complete
bits : 4 - 4 (1 bit)
CRQA0 : channel x request active flag
bits : 16 - 16 (1 bit)
MDMA channel x interrupt/status register
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF15 : Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
bits : 0 - 0 (1 bit)
CTCIF15 : Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0.
bits : 1 - 1 (1 bit)
BRTIF15 : Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
bits : 2 - 2 (1 bit)
BTIF15 : Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
bits : 3 - 3 (1 bit)
TCIF15 : channel x buffer transfer complete
bits : 4 - 4 (1 bit)
CRQA15 : channel x request active flag
bits : 16 - 16 (1 bit)
MDMA channel x interrupt flag clear register
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CTEIF15 : Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register
bits : 0 - 0 (1 bit)
CCTCIF15 : Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register
bits : 1 - 1 (1 bit)
CBRTIF15 : Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register
bits : 2 - 2 (1 bit)
CBTIF15 : Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register
bits : 3 - 3 (1 bit)
CLTCIF15 : CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register
bits : 4 - 4 (1 bit)
MDMA Channel x error status register
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error.
bits : 0 - 6 (7 bit)
TED : Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error.
bits : 7 - 7 (1 bit)
TELD : Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 8 - 8 (1 bit)
TEMD : Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 9 - 9 (1 bit)
ASE : Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 10 - 10 (1 bit)
BSE : Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 11 - 11 (1 bit)
This register is used to control the concerned channel.
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : channel enable
bits : 0 - 0 (1 bit)
access : read-write
TEIE : Transfer error interrupt enable This bit is set and cleared by software.
bits : 1 - 1 (1 bit)
access : read-write
CTCIE : Channel Transfer Complete interrupt enable This bit is set and cleared by software.
bits : 2 - 2 (1 bit)
access : read-write
BRTIE : Block Repeat transfer interrupt enable This bit is set and cleared by software.
bits : 3 - 3 (1 bit)
access : read-write
BTIE : Block Transfer interrupt enable This bit is set and cleared by software.
bits : 4 - 4 (1 bit)
access : read-write
TCIE : buffer Transfer Complete interrupt enable This bit is set and cleared by software.
bits : 5 - 5 (1 bit)
access : read-write
PL : Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0.
bits : 6 - 7 (2 bit)
access : read-write
BEX : byte Endianness exchange
bits : 12 - 12 (1 bit)
access : read-write
HEX : Half word Endianes exchange
bits : 13 - 13 (1 bit)
access : read-write
WEX : Word Endianness exchange
bits : 14 - 14 (1 bit)
access : read-write
SWRQ : SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access).
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel.
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
bits : 0 - 1 (2 bit)
DINC : Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden.
bits : 2 - 3 (2 bit)
SSIZE : Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS < SSIZE and SINC ≠ 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1).
bits : 4 - 5 (2 bit)
DSIZE : Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS < DSIZE and DINC ≠ 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1).
bits : 6 - 7 (2 bit)
SINCOS : source increment offset size
bits : 8 - 9 (2 bit)
DINCOS : Destination increment offset
bits : 10 - 11 (2 bit)
SBURST : source burst transfer configuration
bits : 12 - 14 (3 bit)
DBURST : Destination burst transfer configuration
bits : 15 - 17 (3 bit)
TLEN : buffer transfer lengh
bits : 18 - 24 (7 bit)
PKE : PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0
bits : 25 - 25 (1 bit)
PAM : Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0
bits : 26 - 27 (2 bit)
TRGM : Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0.
bits : 28 - 29 (2 bit)
SWRM : SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0.
bits : 30 - 30 (1 bit)
BWM : Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable.
bits : 31 - 31 (1 bit)
MDMA Channel x block number of data register
address_offset : 0x414 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : block number of data to transfer
bits : 0 - 16 (17 bit)
BRSUM : Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0.
bits : 18 - 18 (1 bit)
BRDUM : Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0.
bits : 19 - 19 (1 bit)
BRC : Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0.
bits : 20 - 31 (12 bit)
MDMA channel x source address register
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : source adr base
bits : 0 - 31 (32 bit)
MDMA channel x destination address register
address_offset : 0x41C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : Destination adr base
bits : 0 - 31 (32 bit)
MDMA channel x Block Repeat address Update register
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : source adresse update value
bits : 0 - 15 (16 bit)
DUV : destination address update
bits : 16 - 31 (16 bit)
MDMA channel x Link Address register
address_offset : 0x424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : Link address register
bits : 0 - 31 (32 bit)
MDMA channel x Trigger and Bus selection Register
address_offset : 0x428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : Trigger selection
bits : 0 - 5 (6 bit)
SBUS : Source BUS select This bit is protected and can be written only if EN is 0.
bits : 16 - 16 (1 bit)
DBUS : Destination BUS slect This bit is protected and can be written only if EN is 0.
bits : 17 - 17 (1 bit)
MDMA channel x Mask address register
address_offset : 0x430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : Mask address
bits : 0 - 31 (32 bit)
MDMA channel x Mask Data register
address_offset : 0x434 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : Mask data
bits : 0 - 31 (32 bit)
MDMA channel x interrupt flag clear register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CTEIF0 : Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register
bits : 0 - 0 (1 bit)
CCTCIF0 : Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register
bits : 1 - 1 (1 bit)
CBRTIF0 : Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register
bits : 2 - 2 (1 bit)
CBTIF0 : Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register
bits : 3 - 3 (1 bit)
CLTCIF0 : CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register
bits : 4 - 4 (1 bit)
MDMA Channel x error status register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error.
bits : 0 - 6 (7 bit)
TED : Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error.
bits : 7 - 7 (1 bit)
TELD : Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 8 - 8 (1 bit)
TEMD : Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 9 - 9 (1 bit)
ASE : Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 10 - 10 (1 bit)
BSE : Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 11 - 11 (1 bit)
This register is used to control the concerned channel.
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : channel enable
bits : 0 - 0 (1 bit)
access : read-write
TEIE : Transfer error interrupt enable This bit is set and cleared by software.
bits : 1 - 1 (1 bit)
access : read-write
CTCIE : Channel Transfer Complete interrupt enable This bit is set and cleared by software.
bits : 2 - 2 (1 bit)
access : read-write
BRTIE : Block Repeat transfer interrupt enable This bit is set and cleared by software.
bits : 3 - 3 (1 bit)
access : read-write
BTIE : Block Transfer interrupt enable This bit is set and cleared by software.
bits : 4 - 4 (1 bit)
access : read-write
TCIE : buffer Transfer Complete interrupt enable This bit is set and cleared by software.
bits : 5 - 5 (1 bit)
access : read-write
PL : Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0.
bits : 6 - 7 (2 bit)
access : read-write
BEX : byte Endianness exchange
bits : 12 - 12 (1 bit)
access : read-write
HEX : Half word Endianes exchange
bits : 13 - 13 (1 bit)
access : read-write
WEX : Word Endianness exchange
bits : 14 - 14 (1 bit)
access : read-write
SWRQ : SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access).
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel.
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
bits : 0 - 1 (2 bit)
DINC : Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden.
bits : 2 - 3 (2 bit)
SSIZE : Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS < SSIZE and SINC ≠ 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1).
bits : 4 - 5 (2 bit)
DSIZE : Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS < DSIZE and DINC ≠ 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1).
bits : 6 - 7 (2 bit)
SINCOS : source increment offset size
bits : 8 - 9 (2 bit)
DINCOS : Destination increment offset
bits : 10 - 11 (2 bit)
SBURST : source burst transfer configuration
bits : 12 - 14 (3 bit)
DBURST : Destination burst transfer configuration
bits : 15 - 17 (3 bit)
TLEN : buffer transfer lengh
bits : 18 - 24 (7 bit)
PKE : PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0
bits : 25 - 25 (1 bit)
PAM : Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0
bits : 26 - 27 (2 bit)
TRGM : Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0.
bits : 28 - 29 (2 bit)
SWRM : SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0.
bits : 30 - 30 (1 bit)
BWM : Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable.
bits : 31 - 31 (1 bit)
MDMA Channel x block number of data register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : block number of data to transfer
bits : 0 - 16 (17 bit)
BRSUM : Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0.
bits : 18 - 18 (1 bit)
BRDUM : Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0.
bits : 19 - 19 (1 bit)
BRC : Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0.
bits : 20 - 31 (12 bit)
MDMA channel x source address register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : source adr base
bits : 0 - 31 (32 bit)
MDMA channel x destination address register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : Destination adr base
bits : 0 - 31 (32 bit)
MDMA channel x Block Repeat address Update register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : source adresse update value
bits : 0 - 15 (16 bit)
DUV : destination address update
bits : 16 - 31 (16 bit)
MDMA channel x Link Address register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : Link address register
bits : 0 - 31 (32 bit)
MDMA channel x Trigger and Bus selection Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : Trigger selection
bits : 0 - 5 (6 bit)
SBUS : Source BUS select This bit is protected and can be written only if EN is 0.
bits : 16 - 16 (1 bit)
DBUS : Destination BUS slect This bit is protected and can be written only if EN is 0.
bits : 17 - 17 (1 bit)
MDMA channel x Mask address register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : Mask address
bits : 0 - 31 (32 bit)
MDMA channel x Mask Data register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : Mask data
bits : 0 - 31 (32 bit)
MDMA channel x interrupt/status register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF1 : Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
bits : 0 - 0 (1 bit)
CTCIF1 : Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0.
bits : 1 - 1 (1 bit)
BRTIF1 : Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
bits : 2 - 2 (1 bit)
BTIF1 : Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
bits : 3 - 3 (1 bit)
TCIF1 : channel x buffer transfer complete
bits : 4 - 4 (1 bit)
CRQA1 : channel x request active flag
bits : 16 - 16 (1 bit)
MDMA channel x interrupt flag clear register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CTEIF1 : Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register
bits : 0 - 0 (1 bit)
CCTCIF1 : Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register
bits : 1 - 1 (1 bit)
CBRTIF1 : Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register
bits : 2 - 2 (1 bit)
CBTIF1 : Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register
bits : 3 - 3 (1 bit)
CLTCIF1 : CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register
bits : 4 - 4 (1 bit)
MDMA Channel x error status register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error.
bits : 0 - 6 (7 bit)
TED : Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error.
bits : 7 - 7 (1 bit)
TELD : Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 8 - 8 (1 bit)
TEMD : Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 9 - 9 (1 bit)
ASE : Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 10 - 10 (1 bit)
BSE : Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 11 - 11 (1 bit)
This register is used to control the concerned channel.
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : channel enable
bits : 0 - 0 (1 bit)
access : read-write
TEIE : Transfer error interrupt enable This bit is set and cleared by software.
bits : 1 - 1 (1 bit)
access : read-write
CTCIE : Channel Transfer Complete interrupt enable This bit is set and cleared by software.
bits : 2 - 2 (1 bit)
access : read-write
BRTIE : Block Repeat transfer interrupt enable This bit is set and cleared by software.
bits : 3 - 3 (1 bit)
access : read-write
BTIE : Block Transfer interrupt enable This bit is set and cleared by software.
bits : 4 - 4 (1 bit)
access : read-write
TCIE : buffer Transfer Complete interrupt enable This bit is set and cleared by software.
bits : 5 - 5 (1 bit)
access : read-write
PL : Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0.
bits : 6 - 7 (2 bit)
access : read-write
BEX : byte Endianness exchange
bits : 12 - 12 (1 bit)
access : read-write
HEX : Half word Endianes exchange
bits : 13 - 13 (1 bit)
access : read-write
WEX : Word Endianness exchange
bits : 14 - 14 (1 bit)
access : read-write
SWRQ : SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access).
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel.
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
bits : 0 - 1 (2 bit)
DINC : Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden.
bits : 2 - 3 (2 bit)
SSIZE : Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS < SSIZE and SINC ≠ 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1).
bits : 4 - 5 (2 bit)
DSIZE : Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS < DSIZE and DINC ≠ 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1).
bits : 6 - 7 (2 bit)
SINCOS : source increment offset size
bits : 8 - 9 (2 bit)
DINCOS : Destination increment offset
bits : 10 - 11 (2 bit)
SBURST : source burst transfer configuration
bits : 12 - 14 (3 bit)
DBURST : Destination burst transfer configuration
bits : 15 - 17 (3 bit)
TLEN : buffer transfer lengh
bits : 18 - 24 (7 bit)
PKE : PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0
bits : 25 - 25 (1 bit)
PAM : Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0
bits : 26 - 27 (2 bit)
TRGM : Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0.
bits : 28 - 29 (2 bit)
SWRM : SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0.
bits : 30 - 30 (1 bit)
BWM : Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable.
bits : 31 - 31 (1 bit)
MDMA Channel x block number of data register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : block number of data to transfer
bits : 0 - 16 (17 bit)
BRSUM : Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0.
bits : 18 - 18 (1 bit)
BRDUM : Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0.
bits : 19 - 19 (1 bit)
BRC : Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0.
bits : 20 - 31 (12 bit)
MDMA channel x source address register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : source adr base
bits : 0 - 31 (32 bit)
MDMA channel x destination address register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : Destination adr base
bits : 0 - 31 (32 bit)
MDMA channel x Block Repeat address Update register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : source adresse update value
bits : 0 - 15 (16 bit)
DUV : destination address update
bits : 16 - 31 (16 bit)
MDMA channel x Link Address register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : Link address register
bits : 0 - 31 (32 bit)
MDMA channel x Trigger and Bus selection Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : Trigger selection
bits : 0 - 5 (6 bit)
SBUS : Source BUS select This bit is protected and can be written only if EN is 0.
bits : 16 - 16 (1 bit)
DBUS : Destination BUS slect This bit is protected and can be written only if EN is 0.
bits : 17 - 17 (1 bit)
MDMA channel x Mask address register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : Mask address
bits : 0 - 31 (32 bit)
MDMA channel x Mask Data register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : Mask data
bits : 0 - 31 (32 bit)
MDMA channel x interrupt/status register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF2 : Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
bits : 0 - 0 (1 bit)
CTCIF2 : Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0.
bits : 1 - 1 (1 bit)
BRTIF2 : Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
bits : 2 - 2 (1 bit)
BTIF2 : Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
bits : 3 - 3 (1 bit)
TCIF2 : channel x buffer transfer complete
bits : 4 - 4 (1 bit)
CRQA2 : channel x request active flag
bits : 16 - 16 (1 bit)
MDMA channel x interrupt flag clear register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CTEIF2 : Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register
bits : 0 - 0 (1 bit)
CCTCIF2 : Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register
bits : 1 - 1 (1 bit)
CBRTIF2 : Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register
bits : 2 - 2 (1 bit)
CBTIF2 : Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register
bits : 3 - 3 (1 bit)
CLTCIF2 : CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register
bits : 4 - 4 (1 bit)
MDMA Channel x error status register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error.
bits : 0 - 6 (7 bit)
TED : Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error.
bits : 7 - 7 (1 bit)
TELD : Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 8 - 8 (1 bit)
TEMD : Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 9 - 9 (1 bit)
ASE : Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 10 - 10 (1 bit)
BSE : Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register.
bits : 11 - 11 (1 bit)
This register is used to control the concerned channel.
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : channel enable
bits : 0 - 0 (1 bit)
access : read-write
TEIE : Transfer error interrupt enable This bit is set and cleared by software.
bits : 1 - 1 (1 bit)
access : read-write
CTCIE : Channel Transfer Complete interrupt enable This bit is set and cleared by software.
bits : 2 - 2 (1 bit)
access : read-write
BRTIE : Block Repeat transfer interrupt enable This bit is set and cleared by software.
bits : 3 - 3 (1 bit)
access : read-write
BTIE : Block Transfer interrupt enable This bit is set and cleared by software.
bits : 4 - 4 (1 bit)
access : read-write
TCIE : buffer Transfer Complete interrupt enable This bit is set and cleared by software.
bits : 5 - 5 (1 bit)
access : read-write
PL : Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0.
bits : 6 - 7 (2 bit)
access : read-write
BEX : byte Endianness exchange
bits : 12 - 12 (1 bit)
access : read-write
HEX : Half word Endianes exchange
bits : 13 - 13 (1 bit)
access : read-write
WEX : Word Endianness exchange
bits : 14 - 14 (1 bit)
access : read-write
SWRQ : SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access).
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel.
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
bits : 0 - 1 (2 bit)
DINC : Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden.
bits : 2 - 3 (2 bit)
SSIZE : Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS < SSIZE and SINC ≠ 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1).
bits : 4 - 5 (2 bit)
DSIZE : Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS < DSIZE and DINC ≠ 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1).
bits : 6 - 7 (2 bit)
SINCOS : source increment offset size
bits : 8 - 9 (2 bit)
DINCOS : Destination increment offset
bits : 10 - 11 (2 bit)
SBURST : source burst transfer configuration
bits : 12 - 14 (3 bit)
DBURST : Destination burst transfer configuration
bits : 15 - 17 (3 bit)
TLEN : buffer transfer lengh
bits : 18 - 24 (7 bit)
PKE : PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0
bits : 25 - 25 (1 bit)
PAM : Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0
bits : 26 - 27 (2 bit)
TRGM : Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0.
bits : 28 - 29 (2 bit)
SWRM : SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0.
bits : 30 - 30 (1 bit)
BWM : Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable.
bits : 31 - 31 (1 bit)
MDMA Channel x block number of data register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : block number of data to transfer
bits : 0 - 16 (17 bit)
BRSUM : Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0.
bits : 18 - 18 (1 bit)
BRDUM : Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0.
bits : 19 - 19 (1 bit)
BRC : Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0.
bits : 20 - 31 (12 bit)
MDMA channel x source address register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : source adr base
bits : 0 - 31 (32 bit)
MDMA channel x destination address register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : Destination adr base
bits : 0 - 31 (32 bit)
MDMA channel x Block Repeat address Update register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : source adresse update value
bits : 0 - 15 (16 bit)
DUV : destination address update
bits : 16 - 31 (16 bit)
MDMA channel x Link Address register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : Link address register
bits : 0 - 31 (32 bit)
MDMA channel x Trigger and Bus selection Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : Trigger selection
bits : 0 - 5 (6 bit)
SBUS : Source BUS select This bit is protected and can be written only if EN is 0.
bits : 16 - 16 (1 bit)
DBUS : Destination BUS slect This bit is protected and can be written only if EN is 0.
bits : 17 - 17 (1 bit)
MDMA channel x Mask address register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : Mask address
bits : 0 - 31 (32 bit)
MDMA channel x Mask Data register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : Mask data
bits : 0 - 31 (32 bit)
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.