\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
Main Clock Control
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCSEL : Main Clock Select
bits : 0 - 2 (3 bit)
PBB Clock Select
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PBSEL : PBB Clock Select
bits : 0 - 2 (3 bit)
PBDIV : PBB Division Select
bits : 7 - 7 (1 bit)
PBC Clock Select
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PBSEL : PBC Clock Select
bits : 0 - 2 (3 bit)
PBDIV : PBC Division Select
bits : 7 - 7 (1 bit)
Peripheral Power Control Register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSTPUN : Reset Pullup
bits : 0 - 0 (1 bit)
CATBRCMASK : CAT Request Clock Mask
bits : 1 - 1 (1 bit)
ACIFCRCMASK : ACIFC Request Clock Mask
bits : 2 - 2 (1 bit)
ASTRCMASK : AST Request Clock Mask
bits : 3 - 3 (1 bit)
TWIS0RCMASK : TWIS0 Request Clock Mask
bits : 4 - 4 (1 bit)
TWIS1RCMASK : TWIS1 Request Clock Mask
bits : 5 - 5 (1 bit)
PEVCRCMASK : PEVC Request Clock Mask
bits : 6 - 6 (1 bit)
ADCIFERCMASK : ADCIFE Request Clock Mask
bits : 7 - 7 (1 bit)
VREGRCMASK : VREG Request Clock Mask
bits : 8 - 8 (1 bit)
FWBGREF : Flash Wait BGREF
bits : 9 - 9 (1 bit)
FWBOD18 : Flash Wait BOD18
bits : 10 - 10 (1 bit)
PBD Clock Select
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PBSEL : PBD Clock Select
bits : 0 - 2 (3 bit)
PBDIV : PBD Division Select
bits : 7 - 7 (1 bit)
Reset Cause Register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
POR : Power-on Reset
bits : 0 - 0 (1 bit)
BOD : Brown-out Reset
bits : 1 - 1 (1 bit)
EXT : External Reset Pin
bits : 2 - 2 (1 bit)
WDT : Watchdog Reset
bits : 3 - 3 (1 bit)
OCDRST : OCD Reset
bits : 8 - 8 (1 bit)
POR33 : Power-on Reset
bits : 10 - 10 (1 bit)
BOD33 : Brown-out 3.3V Reset
bits : 13 - 13 (1 bit)
Wake Cause Register
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TWI_SLAVE_0 : Two-wire Slave Interface 0
bits : 0 - 0 (1 bit)
access : read-only
TWI_SLAVE_1 : Two-wire Slave Interface 1
bits : 1 - 1 (1 bit)
access : read-only
USBC : USB Device and Embedded Host Interface
bits : 2 - 2 (1 bit)
access : read-only
PSOK : Power Scaling OK
bits : 3 - 3 (1 bit)
access : read-only
BOD18_IRQ : BOD18 Interrupt
bits : 4 - 4 (1 bit)
access : read-only
BOD33_IRQ : BOD33 Interrupt
bits : 5 - 5 (1 bit)
access : read-only
PICOUART : Picopower UART
bits : 6 - 6 (1 bit)
access : read-only
LCDCA : LCD Controller
bits : 7 - 7 (1 bit)
access : read-only
EIC : External Interrupt Controller
bits : 16 - 16 (1 bit)
access : read-only
AST : Asynchronous Timer
bits : 17 - 17 (1 bit)
access : read-only
Asynchronous Wake Enable
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AWEN : Asynchronous Wake Up
bits : 0 - 31 (32 bit)
Obsvervability
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Fast Sleep Register
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OSC : Oscillator
bits : 0 - 0 (1 bit)
PLL : PLL
bits : 8 - 8 (1 bit)
FASTRCOSC : RC80 or FLO
bits : 16 - 20 (5 bit)
DFLL : DFLL
bits : 24 - 24 (1 bit)
CPU Mask
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OCD_ : OCD CPU Clock Mask
bits : 0 - 0 (1 bit)
HSB Mask
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDCA_ : PDCA HSB Clock Mask
bits : 0 - 0 (1 bit)
HFLASHC_ : HFLASHC HSB Clock Mask
bits : 1 - 1 (1 bit)
HRAMC1_ : HRAMC1 HSB Clock Mask
bits : 2 - 2 (1 bit)
USBC_ : USBC HSB Clock Mask
bits : 3 - 3 (1 bit)
CRCCU_ : CRCCU HSB Clock Mask
bits : 4 - 4 (1 bit)
HTOP0_ : HTOP0 HSB Clock Mask
bits : 5 - 5 (1 bit)
HTOP1_ : HTOP1 HSB Clock Mask
bits : 6 - 6 (1 bit)
HTOP2_ : HTOP2 HSB Clock Mask
bits : 7 - 7 (1 bit)
HTOP3_ : HTOP3 HSB Clock Mask
bits : 8 - 8 (1 bit)
AESA_ : AESA HSB Clock Mask
bits : 9 - 9 (1 bit)
PBA Mask
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IISC_ : IISC APB Clock Enable
bits : 0 - 0 (1 bit)
SPI_ : SPI APB Clock Enable
bits : 1 - 1 (1 bit)
TC0_ : TC0 APB Clock Enable
bits : 2 - 2 (1 bit)
TC1_ : TC1 APB Clock Enable
bits : 3 - 3 (1 bit)
TWIM0_ : TWIM0 APB Clock Enable
bits : 4 - 4 (1 bit)
TWIS0_ : TWIS0 APB Clock Enable
bits : 5 - 5 (1 bit)
TWIM1_ : TWIM1 APB Clock Enable
bits : 6 - 6 (1 bit)
TWIS1_ : TWIS1 APB Clock Enable
bits : 7 - 7 (1 bit)
USART0_ : USART0 APB Clock Enable
bits : 8 - 8 (1 bit)
USART1_ : USART1 APB Clock Enable
bits : 9 - 9 (1 bit)
USART2_ : USART2 APB Clock Enable
bits : 10 - 10 (1 bit)
USART3_ : USART3 APB Clock Enable
bits : 11 - 11 (1 bit)
ADCIFE_ : ADCIFE APB Clock Enable
bits : 12 - 12 (1 bit)
DACC_ : DACC APB Clock Enable
bits : 13 - 13 (1 bit)
ACIFC_ : ACIFC APB Clock Enable
bits : 14 - 14 (1 bit)
GLOC_ : GLOC APB Clock Enable
bits : 15 - 15 (1 bit)
ABDACB_ : ABDACB APB Clock Enable
bits : 16 - 16 (1 bit)
TRNG_ : TRNG APB Clock Enable
bits : 17 - 17 (1 bit)
PARC_ : PARC APB Clock Enable
bits : 18 - 18 (1 bit)
CATB_ : CATB APB Clock Enable
bits : 19 - 19 (1 bit)
TWIM2_ : TWIM2 APB Clock Enable
bits : 21 - 21 (1 bit)
TWIM3_ : TWIM3 APB Clock Enable
bits : 22 - 22 (1 bit)
LCDCA_ : LCDCA APB Clock Enable
bits : 23 - 23 (1 bit)
PBB Mask
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HFLASHC_ : HFLASHC APB Clock Enable
bits : 0 - 0 (1 bit)
HCACHE_ : HCACHE APB Clock Enable
bits : 1 - 1 (1 bit)
HMATRIX_ : HMATRIX APB Clock Enable
bits : 2 - 2 (1 bit)
PDCA_ : PDCA APB Clock Enable
bits : 3 - 3 (1 bit)
CRCCU_ : CRCCU APB Clock Enable
bits : 4 - 4 (1 bit)
USBC_ : USBC APB Clock Enable
bits : 5 - 5 (1 bit)
PEVC_ : PEVC APB Clock Enable
bits : 6 - 6 (1 bit)
PBC Mask
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PM_ : PM APB Clock Enable
bits : 0 - 0 (1 bit)
CHIPID_ : CHIPID APB Clock Enable
bits : 1 - 1 (1 bit)
SCIF_ : SCIF APB Clock Enable
bits : 2 - 2 (1 bit)
FREQM_ : FREQM APB Clock Enable
bits : 3 - 3 (1 bit)
GPIO_ : GPIO APB Clock Enable
bits : 4 - 4 (1 bit)
PBD Mask
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BPM_ : BPM APB Clock Enable
bits : 0 - 0 (1 bit)
BSCIF_ : BSCIF APB Clock Enable
bits : 1 - 1 (1 bit)
AST_ : AST APB Clock Enable
bits : 2 - 2 (1 bit)
WDT_ : WDT APB Clock Enable
bits : 3 - 3 (1 bit)
EIC_ : EIC APB Clock Enable
bits : 4 - 4 (1 bit)
PICOUART_ : PICOUART APB Clock Enable
bits : 5 - 5 (1 bit)
Configuration Register
address_offset : 0x3F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PBA : APBA Implemented
bits : 0 - 0 (1 bit)
PBB : APBB Implemented
bits : 1 - 1 (1 bit)
PBC : APBC Implemented
bits : 2 - 2 (1 bit)
PBD : APBD Implemented
bits : 3 - 3 (1 bit)
HSBPEVC : HSB PEVC Clock Implemented
bits : 7 - 7 (1 bit)
Version Register
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VERSION : Version number
bits : 0 - 11 (12 bit)
access : read-only
VARIANT : Variant number
bits : 16 - 19 (4 bit)
access : read-only
CPU Clock Select
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPUSEL : CPU Clock Select
bits : 0 - 2 (3 bit)
Enumeration: CPUSELSelect
0x0 : 0
fCPU:fmain. CPUDIV:
0x1 : 1
fCPU:fmain / 2^(CPUSEL+1)
End of enumeration elements list.
CPUDIV : CPU Division
bits : 7 - 7 (1 bit)
PBA Divided Clock Mask
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Clock Failure Detector Control
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFDEN : Clock Failure Detection Enable
bits : 0 - 0 (1 bit)
SFV : Store Final Value
bits : 31 - 31 (1 bit)
Unlock Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
ADDR : Unlock Address
bits : 0 - 9 (10 bit)
KEY : Unlock Key
bits : 24 - 31 (8 bit)
PBA Clock Select
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PBSEL : PBA Clock Select
bits : 0 - 2 (3 bit)
PBDIV : PBA Division Select
bits : 7 - 7 (1 bit)
Interrupt Enable Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CFD : Clock Failure Detected Interrupt Enable
bits : 0 - 0 (1 bit)
CKRDY : Clock Ready Interrupt Enable
bits : 5 - 5 (1 bit)
WAKE : Wake up Interrupt Enable
bits : 8 - 8 (1 bit)
Enumeration: WAKESelect
0x0 : 0
No effect
0x1 : 1
Disable Interrupt.
End of enumeration elements list.
AE : Access Error Interrupt Enable
bits : 31 - 31 (1 bit)
Interrupt Disable Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CFD : Clock Failure Detected Interrupt Disable
bits : 0 - 0 (1 bit)
CKRDY : Clock Ready Interrupt Disable
bits : 5 - 5 (1 bit)
WAKE : Wake up Interrupt Disable
bits : 8 - 8 (1 bit)
Enumeration: WAKESelect
0x0 : 0
No effect
0x1 : 1
Disable Interrupt.
End of enumeration elements list.
AE : Access Error Interrupt Disable
bits : 31 - 31 (1 bit)
Interrupt Mask Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CFD : Clock Failure Detected Interrupt Mask
bits : 0 - 0 (1 bit)
CKRDY : Clock Ready Interrupt Mask
bits : 5 - 5 (1 bit)
WAKE : Wake up Interrupt Mask
bits : 8 - 8 (1 bit)
Enumeration: WAKESelect
0x0 : 0
No effect
0x1 : 1
Disable Interrupt.
End of enumeration elements list.
AE : Access Error Interrupt Mask
bits : 31 - 31 (1 bit)
Interrupt Status Register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CFD : Clock Failure Detected Interrupt Status
bits : 0 - 0 (1 bit)
CKRDY : Clock Ready Interrupt Status
bits : 5 - 5 (1 bit)
WAKE : Wake up Interrupt Status
bits : 8 - 8 (1 bit)
Enumeration: WAKESelect
0x0 : 0
No effect
0x1 : 1
Disable Interrupt.
End of enumeration elements list.
AE : Access Error Interrupt Status
bits : 31 - 31 (1 bit)
Interrupt Clear Register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CFD : Clock Failure Detected Interrupt Status Clear
bits : 0 - 0 (1 bit)
CKRDY : Clock Ready Interrupt Status Clear
bits : 5 - 5 (1 bit)
WAKE : Wake up Interrupt Status Clear
bits : 8 - 8 (1 bit)
AE : Access Error Interrupt Status Clear
bits : 31 - 31 (1 bit)
Status Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CFD : Clock Failure Detected
bits : 0 - 0 (1 bit)
OCP : Over Clock Detected
bits : 1 - 1 (1 bit)
CKRDY : Clock Ready
bits : 5 - 5 (1 bit)
WAKE : Wake up
bits : 8 - 8 (1 bit)
Enumeration: WAKESelect
0x0 : 0
No effect
0x1 : 1
Disable Interrupt.
End of enumeration elements list.
PERRDY : Peripheral Ready
bits : 28 - 28 (1 bit)
AE : Access Error
bits : 31 - 31 (1 bit)
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