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address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
DMAMux - DMA request line multiplexer channel x control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAREQ_ID : Input DMA request line selected
bits : 0 - 7 (8 bit)
SOIE : Interrupt enable at synchronization event overrun
bits : 8 - 8 (1 bit)
EGE : Event generation enable/disable
bits : 9 - 9 (1 bit)
SE : Synchronous operating mode enable/disable
bits : 16 - 16 (1 bit)
SPOL : Synchronization event type selector Defines the synchronization event on the selected synchronization input:
bits : 17 - 18 (2 bit)
NBREQ : Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
bits : 19 - 23 (5 bit)
SYNC_ID : Synchronization input selected
bits : 24 - 28 (5 bit)
DMAMux - DMA request line multiplexer channel x control register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAREQ_ID : Input DMA request line selected
bits : 0 - 7 (8 bit)
SOIE : Interrupt enable at synchronization event overrun
bits : 8 - 8 (1 bit)
EGE : Event generation enable/disable
bits : 9 - 9 (1 bit)
SE : Synchronous operating mode enable/disable
bits : 16 - 16 (1 bit)
SPOL : Synchronization event type selector Defines the synchronization event on the selected synchronization input:
bits : 17 - 18 (2 bit)
NBREQ : Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
bits : 19 - 23 (5 bit)
SYNC_ID : Synchronization input selected
bits : 24 - 28 (5 bit)
DMAMux - DMA request generator channel x control register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIG_ID : DMA request trigger input selected
bits : 0 - 4 (5 bit)
OIE : Interrupt enable at trigger event overrun
bits : 8 - 8 (1 bit)
GE : DMA request generator channel enable/disable
bits : 16 - 16 (1 bit)
GPOL : DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input
bits : 17 - 18 (2 bit)
GNBREQ : Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.
bits : 19 - 23 (5 bit)
DMAMux - DMA request generator channel x control register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIG_ID : DMA request trigger input selected
bits : 0 - 4 (5 bit)
OIE : Interrupt enable at trigger event overrun
bits : 8 - 8 (1 bit)
GE : DMA request generator channel enable/disable
bits : 16 - 16 (1 bit)
GPOL : DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input
bits : 17 - 18 (2 bit)
GNBREQ : Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.
bits : 19 - 23 (5 bit)
DMAMux - DMA request generator channel x control register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIG_ID : DMA request trigger input selected
bits : 0 - 4 (5 bit)
OIE : Interrupt enable at trigger event overrun
bits : 8 - 8 (1 bit)
GE : DMA request generator channel enable/disable
bits : 16 - 16 (1 bit)
GPOL : DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input
bits : 17 - 18 (2 bit)
GNBREQ : Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.
bits : 19 - 23 (5 bit)
DMAMux - DMA request generator channel x control register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIG_ID : DMA request trigger input selected
bits : 0 - 4 (5 bit)
OIE : Interrupt enable at trigger event overrun
bits : 8 - 8 (1 bit)
GE : DMA request generator channel enable/disable
bits : 16 - 16 (1 bit)
GPOL : DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input
bits : 17 - 18 (2 bit)
GNBREQ : Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.
bits : 19 - 23 (5 bit)
DMAMux - DMA request generator channel x control register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIG_ID : DMA request trigger input selected
bits : 0 - 4 (5 bit)
OIE : Interrupt enable at trigger event overrun
bits : 8 - 8 (1 bit)
GE : DMA request generator channel enable/disable
bits : 16 - 16 (1 bit)
GPOL : DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input
bits : 17 - 18 (2 bit)
GNBREQ : Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.
bits : 19 - 23 (5 bit)
DMAMux - DMA request generator channel x control register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIG_ID : DMA request trigger input selected
bits : 0 - 4 (5 bit)
OIE : Interrupt enable at trigger event overrun
bits : 8 - 8 (1 bit)
GE : DMA request generator channel enable/disable
bits : 16 - 16 (1 bit)
GPOL : DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input
bits : 17 - 18 (2 bit)
GNBREQ : Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.
bits : 19 - 23 (5 bit)
DMAMux - DMA request generator channel x control register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIG_ID : DMA request trigger input selected
bits : 0 - 4 (5 bit)
OIE : Interrupt enable at trigger event overrun
bits : 8 - 8 (1 bit)
GE : DMA request generator channel enable/disable
bits : 16 - 16 (1 bit)
GPOL : DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input
bits : 17 - 18 (2 bit)
GNBREQ : Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.
bits : 19 - 23 (5 bit)
DMAMux - DMA request generator channel x control register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIG_ID : DMA request trigger input selected
bits : 0 - 4 (5 bit)
OIE : Interrupt enable at trigger event overrun
bits : 8 - 8 (1 bit)
GE : DMA request generator channel enable/disable
bits : 16 - 16 (1 bit)
GPOL : DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input
bits : 17 - 18 (2 bit)
GNBREQ : Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.
bits : 19 - 23 (5 bit)
DMAMux - DMA request line multiplexer channel x control register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAREQ_ID : Input DMA request line selected
bits : 0 - 7 (8 bit)
SOIE : Interrupt enable at synchronization event overrun
bits : 8 - 8 (1 bit)
EGE : Event generation enable/disable
bits : 9 - 9 (1 bit)
SE : Synchronous operating mode enable/disable
bits : 16 - 16 (1 bit)
SPOL : Synchronization event type selector Defines the synchronization event on the selected synchronization input:
bits : 17 - 18 (2 bit)
NBREQ : Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
bits : 19 - 23 (5 bit)
SYNC_ID : Synchronization input selected
bits : 24 - 28 (5 bit)
DMAMux - DMA request generator status register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
OF : Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register.
bits : 0 - 7 (8 bit)
DMAMux - DMA request generator clear flag register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
COF : Clear trigger event overrun flag Upon setting, this bit clears the corresponding overrun flag OFx in the DMAMUX_RGCSR register.
bits : 0 - 7 (8 bit)
DMAMux - DMA request line multiplexer channel x control register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAREQ_ID : Input DMA request line selected
bits : 0 - 7 (8 bit)
SOIE : Interrupt enable at synchronization event overrun
bits : 8 - 8 (1 bit)
EGE : Event generation enable/disable
bits : 9 - 9 (1 bit)
SE : Synchronous operating mode enable/disable
bits : 16 - 16 (1 bit)
SPOL : Synchronization event type selector Defines the synchronization event on the selected synchronization input:
bits : 17 - 18 (2 bit)
NBREQ : Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
bits : 19 - 23 (5 bit)
SYNC_ID : Synchronization input selected
bits : 24 - 28 (5 bit)
DMAMux - DMA request line multiplexer channel x control register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAREQ_ID : Input DMA request line selected
bits : 0 - 7 (8 bit)
SOIE : Interrupt enable at synchronization event overrun
bits : 8 - 8 (1 bit)
EGE : Event generation enable/disable
bits : 9 - 9 (1 bit)
SE : Synchronous operating mode enable/disable
bits : 16 - 16 (1 bit)
SPOL : Synchronization event type selector Defines the synchronization event on the selected synchronization input:
bits : 17 - 18 (2 bit)
NBREQ : Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
bits : 19 - 23 (5 bit)
SYNC_ID : Synchronization input selected
bits : 24 - 28 (5 bit)
DMAMux - DMA request line multiplexer channel x control register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAREQ_ID : Input DMA request line selected
bits : 0 - 7 (8 bit)
SOIE : Interrupt enable at synchronization event overrun
bits : 8 - 8 (1 bit)
EGE : Event generation enable/disable
bits : 9 - 9 (1 bit)
SE : Synchronous operating mode enable/disable
bits : 16 - 16 (1 bit)
SPOL : Synchronization event type selector Defines the synchronization event on the selected synchronization input:
bits : 17 - 18 (2 bit)
NBREQ : Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
bits : 19 - 23 (5 bit)
SYNC_ID : Synchronization input selected
bits : 24 - 28 (5 bit)
DMAMux - DMA request line multiplexer channel x control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAREQ_ID : Input DMA request line selected
bits : 0 - 7 (8 bit)
SOIE : Interrupt enable at synchronization event overrun
bits : 8 - 8 (1 bit)
EGE : Event generation enable/disable
bits : 9 - 9 (1 bit)
SE : Synchronous operating mode enable/disable
bits : 16 - 16 (1 bit)
SPOL : Synchronization event type selector Defines the synchronization event on the selected synchronization input:
bits : 17 - 18 (2 bit)
NBREQ : Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
bits : 19 - 23 (5 bit)
SYNC_ID : Synchronization input selected
bits : 24 - 28 (5 bit)
DMAMUX request line multiplexer interrupt channel status register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SOF : Synchronization overrun event flag
bits : 0 - 15 (16 bit)
DMAMUX request line multiplexer interrupt clear flag register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CSOF : Clear synchronization overrun event flag
bits : 0 - 15 (16 bit)
DMAMux - DMA request line multiplexer channel x control register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAREQ_ID : Input DMA request line selected
bits : 0 - 7 (8 bit)
SOIE : Interrupt enable at synchronization event overrun
bits : 8 - 8 (1 bit)
EGE : Event generation enable/disable
bits : 9 - 9 (1 bit)
SE : Synchronous operating mode enable/disable
bits : 16 - 16 (1 bit)
SPOL : Synchronization event type selector Defines the synchronization event on the selected synchronization input:
bits : 17 - 18 (2 bit)
NBREQ : Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
bits : 19 - 23 (5 bit)
SYNC_ID : Synchronization input selected
bits : 24 - 28 (5 bit)
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