\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
VREFBUF control and status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENVR : Voltage reference buffer mode enable This bit is used to enable the voltage reference buffer mode.
bits : 0 - 0 (1 bit)
access : read-write
HIZ : High impedance mode This bit controls the analog switch to connect or not the VREF+ pin. Refer to Table196: VREF buffer modes for the mode descriptions depending on ENVR bit configuration.
bits : 1 - 1 (1 bit)
access : read-write
VRR : Voltage reference buffer ready
bits : 3 - 3 (1 bit)
access : read-only
VRS : Voltage reference scale These bits select the value generated by the voltage reference buffer. Other: Reserved
bits : 4 - 6 (3 bit)
access : read-write
VREFBUF calibration control register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIM : Trimming code These bits are automatically initialized after reset with the trimming value stored in the Flash memory during the production test. Writing into these bits allows to tune the internal reference buffer voltage.
bits : 0 - 5 (6 bit)
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