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BDMA

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

BDMA_ISR (ISR)

BDMA_CPAR0 (CPAR0)

BDMA_CM0AR0 (CM0AR0)

BDMA_CM1AR0 (CM1AR0)

BDMA_CCR1 (CCR1)

BDMA_CNDTR1 (CNDTR1)

BDMA_CPAR1 (CPAR1)

BDMA_CM0AR1 (CM0AR1)

BDMA_CM1AR1 (CM1AR1)

BDMA_CCR2 (CCR2)

BDMA_CNDTR2 (CNDTR2)

BDMA_CPAR2 (CPAR2)

BDMA_CM0AR2 (CM0AR2)

BDMA_IFCR (IFCR)

BDMA_CM1AR2 (CM1AR2)

BDMA_CCR3 (CCR3)

BDMA_CNDTR3 (CNDTR3)

BDMA_CPAR3 (CPAR3)

BDMA_CM0AR3 (CM0AR3)

BDMA_CM1AR3 (CM1AR3)

BDMA_CCR4 (CCR4)

BDMA_CNDTR4 (CNDTR4)

BDMA_CPAR4 (CPAR4)

BDMA_CM0AR4 (CM0AR4)

BDMA_CM1AR4 (CM1AR4)

BDMA_CCR5 (CCR5)

BDMA_CNDTR5 (CNDTR5)

BDMA_CPAR5 (CPAR5)

BDMA_CM0AR5 (CM0AR5)

BDMA_CM1AR5 (CM1AR5)

BDMA_CCR0 (CCR0)

BDMA_CCR6 (CCR6)

BDMA_CNDTR6 (CNDTR6)

BDMA_CPAR6 (CPAR6)

BDMA_CM0AR6 (CM0AR6)

BDMA_CM1AR6 (CM1AR6)

BDMA_CCR7 (CCR7)

BDMA_CNDTR7 (CNDTR7)

BDMA_CPAR7 (CPAR7)

BDMA_CM0AR7 (CM0AR7)

BDMA_CM1AR7 (CM1AR7)

BDMA_CNDTR0 (CNDTR0)


BDMA_ISR (ISR)

DMA interrupt status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BDMA_ISR BDMA_ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GIF1 TCIF1 HTIF1 TEIF1 GIF2 TCIF2 HTIF2 TEIF2 GIF3 TCIF3 HTIF3 TEIF3 GIF4 TCIF4 HTIF4 TEIF4 GIF5 TCIF5 HTIF5 TEIF5 GIF6 TCIF6 HTIF6 TEIF6 GIF7 TCIF7 HTIF7 TEIF7 GIF8 TCIF8 HTIF8 TEIF8

GIF1 : Channel x global interrupt flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 0 - 0 (1 bit)

TCIF1 : Channel x transfer complete flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 1 - 1 (1 bit)

HTIF1 : Channel x half transfer flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 2 - 2 (1 bit)

TEIF1 : Channel x transfer error flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 3 - 3 (1 bit)

GIF2 : Channel x global interrupt flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 4 - 4 (1 bit)

TCIF2 : Channel x transfer complete flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 5 - 5 (1 bit)

HTIF2 : Channel x half transfer flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 6 - 6 (1 bit)

TEIF2 : Channel x transfer error flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 7 - 7 (1 bit)

GIF3 : Channel x global interrupt flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 8 - 8 (1 bit)

TCIF3 : Channel x transfer complete flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 9 - 9 (1 bit)

HTIF3 : Channel x half transfer flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 10 - 10 (1 bit)

TEIF3 : Channel x transfer error flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 11 - 11 (1 bit)

GIF4 : Channel x global interrupt flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 12 - 12 (1 bit)

TCIF4 : Channel x transfer complete flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 13 - 13 (1 bit)

HTIF4 : Channel x half transfer flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 14 - 14 (1 bit)

TEIF4 : Channel x transfer error flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 15 - 15 (1 bit)

GIF5 : Channel x global interrupt flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 16 - 16 (1 bit)

TCIF5 : Channel x transfer complete flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 17 - 17 (1 bit)

HTIF5 : Channel x half transfer flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 18 - 18 (1 bit)

TEIF5 : Channel x transfer error flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 19 - 19 (1 bit)

GIF6 : Channel x global interrupt flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 20 - 20 (1 bit)

TCIF6 : Channel x transfer complete flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 21 - 21 (1 bit)

HTIF6 : Channel x half transfer flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 22 - 22 (1 bit)

TEIF6 : Channel x transfer error flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 23 - 23 (1 bit)

GIF7 : Channel x global interrupt flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 24 - 24 (1 bit)

TCIF7 : Channel x transfer complete flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 25 - 25 (1 bit)

HTIF7 : Channel x half transfer flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 26 - 26 (1 bit)

TEIF7 : Channel x transfer error flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 27 - 27 (1 bit)

GIF8 : Channel x global interrupt flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 28 - 28 (1 bit)

TCIF8 : Channel x transfer complete flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 29 - 29 (1 bit)

HTIF8 : Channel x half transfer flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 30 - 30 (1 bit)

TEIF8 : Channel x transfer error flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 31 - 31 (1 bit)


BDMA_CPAR0 (CPAR0)

This register must not be written when the channel is enabled.
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDMA_CPAR0 BDMA_CPAR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA

PA : Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a half-word address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address.
bits : 0 - 31 (32 bit)


BDMA_CM0AR0 (CM0AR0)

This register must not be written when the channel is enabled.
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDMA_CM0AR0 BDMA_CM0AR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA

MA : Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a half-word address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address.
bits : 0 - 31 (32 bit)


BDMA_CM1AR0 (CM1AR0)

BDMA channel x memory 1 address register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDMA_CM1AR0 BDMA_CM1AR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BDMA_CCR1 (CCR1)

DMA channel x configuration register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDMA_CCR1 BDMA_CCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN TCIE HTIE TEIE DIR CIRC PINC MINC PSIZE MSIZE PL MEM2MEM DBM CT

EN : Channel enable This bit is set and cleared by software.
bits : 0 - 0 (1 bit)

TCIE : Transfer complete interrupt enable This bit is set and cleared by software.
bits : 1 - 1 (1 bit)

HTIE : Half transfer interrupt enable This bit is set and cleared by software.
bits : 2 - 2 (1 bit)

TEIE : Transfer error interrupt enable This bit is set and cleared by software.
bits : 3 - 3 (1 bit)

DIR : Data transfer direction This bit is set and cleared by software.
bits : 4 - 4 (1 bit)

CIRC : Circular mode This bit is set and cleared by software.
bits : 5 - 5 (1 bit)

PINC : Peripheral increment mode This bit is set and cleared by software.
bits : 6 - 6 (1 bit)

MINC : Memory increment mode This bit is set and cleared by software.
bits : 7 - 7 (1 bit)

PSIZE : Peripheral size These bits are set and cleared by software.
bits : 8 - 9 (2 bit)

MSIZE : Memory size These bits are set and cleared by software.
bits : 10 - 11 (2 bit)

PL : Channel priority level These bits are set and cleared by software.
bits : 12 - 13 (2 bit)

MEM2MEM : Memory to memory mode This bit is set and cleared by software.
bits : 14 - 14 (1 bit)

DBM : double-buffer mode
bits : 15 - 15 (1 bit)

CT : current target memory of DMA transfer in double-buffer mode
bits : 16 - 16 (1 bit)


BDMA_CNDTR1 (CNDTR1)

DMA channel x number of data register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDMA_CNDTR1 BDMA_CNDTR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT

NDT : Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not.
bits : 0 - 15 (16 bit)


BDMA_CPAR1 (CPAR1)

This register must not be written when the channel is enabled.
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDMA_CPAR1 BDMA_CPAR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA

PA : Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a half-word address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address.
bits : 0 - 31 (32 bit)


BDMA_CM0AR1 (CM0AR1)

This register must not be written when the channel is enabled.
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDMA_CM0AR1 BDMA_CM0AR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA

MA : Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a half-word address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address.
bits : 0 - 31 (32 bit)


BDMA_CM1AR1 (CM1AR1)

BDMA channel x memory 1 address register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDMA_CM1AR1 BDMA_CM1AR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BDMA_CCR2 (CCR2)

DMA channel x configuration register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDMA_CCR2 BDMA_CCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN TCIE HTIE TEIE DIR CIRC PINC MINC PSIZE MSIZE PL MEM2MEM DBM CT

EN : Channel enable This bit is set and cleared by software.
bits : 0 - 0 (1 bit)

TCIE : Transfer complete interrupt enable This bit is set and cleared by software.
bits : 1 - 1 (1 bit)

HTIE : Half transfer interrupt enable This bit is set and cleared by software.
bits : 2 - 2 (1 bit)

TEIE : Transfer error interrupt enable This bit is set and cleared by software.
bits : 3 - 3 (1 bit)

DIR : Data transfer direction This bit is set and cleared by software.
bits : 4 - 4 (1 bit)

CIRC : Circular mode This bit is set and cleared by software.
bits : 5 - 5 (1 bit)

PINC : Peripheral increment mode This bit is set and cleared by software.
bits : 6 - 6 (1 bit)

MINC : Memory increment mode This bit is set and cleared by software.
bits : 7 - 7 (1 bit)

PSIZE : Peripheral size These bits are set and cleared by software.
bits : 8 - 9 (2 bit)

MSIZE : Memory size These bits are set and cleared by software.
bits : 10 - 11 (2 bit)

PL : Channel priority level These bits are set and cleared by software.
bits : 12 - 13 (2 bit)

MEM2MEM : Memory to memory mode This bit is set and cleared by software.
bits : 14 - 14 (1 bit)

DBM : double-buffer mode
bits : 15 - 15 (1 bit)

CT : current target memory of DMA transfer in double-buffer mode
bits : 16 - 16 (1 bit)


BDMA_CNDTR2 (CNDTR2)

DMA channel x number of data register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDMA_CNDTR2 BDMA_CNDTR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT

NDT : Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not.
bits : 0 - 15 (16 bit)


BDMA_CPAR2 (CPAR2)

This register must not be written when the channel is enabled.
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDMA_CPAR2 BDMA_CPAR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA

PA : Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a half-word address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address.
bits : 0 - 31 (32 bit)


BDMA_CM0AR2 (CM0AR2)

This register must not be written when the channel is enabled.
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDMA_CM0AR2 BDMA_CM0AR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA

MA : Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a half-word address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address.
bits : 0 - 31 (32 bit)


BDMA_IFCR (IFCR)

DMA interrupt flag clear register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

BDMA_IFCR BDMA_IFCR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CGIF1 CTCIF1 CHTIF1 CTEIF1 CGIF2 CTCIF2 CHTIF2 CTEIF2 CGIF3 CTCIF3 CHTIF3 CTEIF3 CGIF4 CTCIF4 CHTIF4 CTEIF4 CGIF5 CTCIF5 CHTIF5 CTEIF5 CGIF6 CTCIF6 CHTIF6 CTEIF6 CGIF7 CTCIF7 CHTIF7 CTEIF7 CGIF8 CTCIF8 CHTIF8 CTEIF8

CGIF1 : Channel x global interrupt clear This bit is set and cleared by software.
bits : 0 - 0 (1 bit)

CTCIF1 : Channel x transfer complete clear This bit is set and cleared by software.
bits : 1 - 1 (1 bit)

CHTIF1 : Channel x half transfer clear This bit is set and cleared by software.
bits : 2 - 2 (1 bit)

CTEIF1 : Channel x transfer error clear This bit is set and cleared by software.
bits : 3 - 3 (1 bit)

CGIF2 : Channel x global interrupt clear This bit is set and cleared by software.
bits : 4 - 4 (1 bit)

CTCIF2 : Channel x transfer complete clear This bit is set and cleared by software.
bits : 5 - 5 (1 bit)

CHTIF2 : Channel x half transfer clear This bit is set and cleared by software.
bits : 6 - 6 (1 bit)

CTEIF2 : Channel x transfer error clear This bit is set and cleared by software.
bits : 7 - 7 (1 bit)

CGIF3 : Channel x global interrupt clear This bit is set and cleared by software.
bits : 8 - 8 (1 bit)

CTCIF3 : Channel x transfer complete clear This bit is set and cleared by software.
bits : 9 - 9 (1 bit)

CHTIF3 : Channel x half transfer clear This bit is set and cleared by software.
bits : 10 - 10 (1 bit)

CTEIF3 : Channel x transfer error clear This bit is set and cleared by software.
bits : 11 - 11 (1 bit)

CGIF4 : Channel x global interrupt clear This bit is set and cleared by software.
bits : 12 - 12 (1 bit)

CTCIF4 : Channel x transfer complete clear This bit is set and cleared by software.
bits : 13 - 13 (1 bit)

CHTIF4 : Channel x half transfer clear This bit is set and cleared by software.
bits : 14 - 14 (1 bit)

CTEIF4 : Channel x transfer error clear This bit is set and cleared by software.
bits : 15 - 15 (1 bit)

CGIF5 : Channel x global interrupt clear This bit is set and cleared by software.
bits : 16 - 16 (1 bit)

CTCIF5 : Channel x transfer complete clear This bit is set and cleared by software.
bits : 17 - 17 (1 bit)

CHTIF5 : Channel x half transfer clear This bit is set and cleared by software.
bits : 18 - 18 (1 bit)

CTEIF5 : Channel x transfer error clear This bit is set and cleared by software.
bits : 19 - 19 (1 bit)

CGIF6 : Channel x global interrupt clear This bit is set and cleared by software.
bits : 20 - 20 (1 bit)

CTCIF6 : Channel x transfer complete clear This bit is set and cleared by software.
bits : 21 - 21 (1 bit)

CHTIF6 : Channel x half transfer clear This bit is set and cleared by software.
bits : 22 - 22 (1 bit)

CTEIF6 : Channel x transfer error clear This bit is set and cleared by software.
bits : 23 - 23 (1 bit)

CGIF7 : Channel x global interrupt clear This bit is set and cleared by software.
bits : 24 - 24 (1 bit)

CTCIF7 : Channel x transfer complete clear This bit is set and cleared by software.
bits : 25 - 25 (1 bit)

CHTIF7 : Channel x half transfer clear This bit is set and cleared by software.
bits : 26 - 26 (1 bit)

CTEIF7 : Channel x transfer error clear This bit is set and cleared by software.
bits : 27 - 27 (1 bit)

CGIF8 : Channel x global interrupt clear This bit is set and cleared by software.
bits : 28 - 28 (1 bit)

CTCIF8 : Channel x transfer complete clear This bit is set and cleared by software.
bits : 29 - 29 (1 bit)

CHTIF8 : Channel x half transfer clear This bit is set and cleared by software.
bits : 30 - 30 (1 bit)

CTEIF8 : Channel x transfer error clear This bit is set and cleared by software.
bits : 31 - 31 (1 bit)


BDMA_CM1AR2 (CM1AR2)

BDMA channel x memory 1 address register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDMA_CM1AR2 BDMA_CM1AR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BDMA_CCR3 (CCR3)

DMA channel x configuration register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDMA_CCR3 BDMA_CCR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN TCIE HTIE TEIE DIR CIRC PINC MINC PSIZE MSIZE PL MEM2MEM DBM CT

EN : Channel enable This bit is set and cleared by software.
bits : 0 - 0 (1 bit)

TCIE : Transfer complete interrupt enable This bit is set and cleared by software.
bits : 1 - 1 (1 bit)

HTIE : Half transfer interrupt enable This bit is set and cleared by software.
bits : 2 - 2 (1 bit)

TEIE : Transfer error interrupt enable This bit is set and cleared by software.
bits : 3 - 3 (1 bit)

DIR : Data transfer direction This bit is set and cleared by software.
bits : 4 - 4 (1 bit)

CIRC : Circular mode This bit is set and cleared by software.
bits : 5 - 5 (1 bit)

PINC : Peripheral increment mode This bit is set and cleared by software.
bits : 6 - 6 (1 bit)

MINC : Memory increment mode This bit is set and cleared by software.
bits : 7 - 7 (1 bit)

PSIZE : Peripheral size These bits are set and cleared by software.
bits : 8 - 9 (2 bit)

MSIZE : Memory size These bits are set and cleared by software.
bits : 10 - 11 (2 bit)

PL : Channel priority level These bits are set and cleared by software.
bits : 12 - 13 (2 bit)

MEM2MEM : Memory to memory mode This bit is set and cleared by software.
bits : 14 - 14 (1 bit)

DBM : double-buffer mode
bits : 15 - 15 (1 bit)

CT : current target memory of DMA transfer in double-buffer mode
bits : 16 - 16 (1 bit)


BDMA_CNDTR3 (CNDTR3)

DMA channel x number of data register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDMA_CNDTR3 BDMA_CNDTR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT

NDT : Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not.
bits : 0 - 15 (16 bit)


BDMA_CPAR3 (CPAR3)

This register must not be written when the channel is enabled.
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDMA_CPAR3 BDMA_CPAR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA

PA : Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a half-word address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address.
bits : 0 - 31 (32 bit)


BDMA_CM0AR3 (CM0AR3)

This register must not be written when the channel is enabled.
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDMA_CM0AR3 BDMA_CM0AR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA

MA : Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a half-word address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address.
bits : 0 - 31 (32 bit)


BDMA_CM1AR3 (CM1AR3)

BDMA channel x memory 1 address register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDMA_CM1AR3 BDMA_CM1AR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BDMA_CCR4 (CCR4)

DMA channel x configuration register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDMA_CCR4 BDMA_CCR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN TCIE HTIE TEIE DIR CIRC PINC MINC PSIZE MSIZE PL MEM2MEM DBM CT

EN : Channel enable This bit is set and cleared by software.
bits : 0 - 0 (1 bit)

TCIE : Transfer complete interrupt enable This bit is set and cleared by software.
bits : 1 - 1 (1 bit)

HTIE : Half transfer interrupt enable This bit is set and cleared by software.
bits : 2 - 2 (1 bit)

TEIE : Transfer error interrupt enable This bit is set and cleared by software.
bits : 3 - 3 (1 bit)

DIR : Data transfer direction This bit is set and cleared by software.
bits : 4 - 4 (1 bit)

CIRC : Circular mode This bit is set and cleared by software.
bits : 5 - 5 (1 bit)

PINC : Peripheral increment mode This bit is set and cleared by software.
bits : 6 - 6 (1 bit)

MINC : Memory increment mode This bit is set and cleared by software.
bits : 7 - 7 (1 bit)

PSIZE : Peripheral size These bits are set and cleared by software.
bits : 8 - 9 (2 bit)

MSIZE : Memory size These bits are set and cleared by software.
bits : 10 - 11 (2 bit)

PL : Channel priority level These bits are set and cleared by software.
bits : 12 - 13 (2 bit)

MEM2MEM : Memory to memory mode This bit is set and cleared by software.
bits : 14 - 14 (1 bit)

DBM : double-buffer mode
bits : 15 - 15 (1 bit)

CT : current target memory of DMA transfer in double-buffer mode
bits : 16 - 16 (1 bit)


BDMA_CNDTR4 (CNDTR4)

DMA channel x number of data register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDMA_CNDTR4 BDMA_CNDTR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT

NDT : Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not.
bits : 0 - 15 (16 bit)


BDMA_CPAR4 (CPAR4)

This register must not be written when the channel is enabled.
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDMA_CPAR4 BDMA_CPAR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA

PA : Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a half-word address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address.
bits : 0 - 31 (32 bit)


BDMA_CM0AR4 (CM0AR4)

This register must not be written when the channel is enabled.
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDMA_CM0AR4 BDMA_CM0AR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA

MA : Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a half-word address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address.
bits : 0 - 31 (32 bit)


BDMA_CM1AR4 (CM1AR4)

BDMA channel x memory 1 address register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDMA_CM1AR4 BDMA_CM1AR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BDMA_CCR5 (CCR5)

DMA channel x configuration register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDMA_CCR5 BDMA_CCR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN TCIE HTIE TEIE DIR CIRC PINC MINC PSIZE MSIZE PL MEM2MEM DBM CT

EN : Channel enable This bit is set and cleared by software.
bits : 0 - 0 (1 bit)

TCIE : Transfer complete interrupt enable This bit is set and cleared by software.
bits : 1 - 1 (1 bit)

HTIE : Half transfer interrupt enable This bit is set and cleared by software.
bits : 2 - 2 (1 bit)

TEIE : Transfer error interrupt enable This bit is set and cleared by software.
bits : 3 - 3 (1 bit)

DIR : Data transfer direction This bit is set and cleared by software.
bits : 4 - 4 (1 bit)

CIRC : Circular mode This bit is set and cleared by software.
bits : 5 - 5 (1 bit)

PINC : Peripheral increment mode This bit is set and cleared by software.
bits : 6 - 6 (1 bit)

MINC : Memory increment mode This bit is set and cleared by software.
bits : 7 - 7 (1 bit)

PSIZE : Peripheral size These bits are set and cleared by software.
bits : 8 - 9 (2 bit)

MSIZE : Memory size These bits are set and cleared by software.
bits : 10 - 11 (2 bit)

PL : Channel priority level These bits are set and cleared by software.
bits : 12 - 13 (2 bit)

MEM2MEM : Memory to memory mode This bit is set and cleared by software.
bits : 14 - 14 (1 bit)

DBM : double-buffer mode
bits : 15 - 15 (1 bit)

CT : current target memory of DMA transfer in double-buffer mode
bits : 16 - 16 (1 bit)


BDMA_CNDTR5 (CNDTR5)

DMA channel x number of data register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDMA_CNDTR5 BDMA_CNDTR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT

NDT : Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not.
bits : 0 - 15 (16 bit)


BDMA_CPAR5 (CPAR5)

This register must not be written when the channel is enabled.
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDMA_CPAR5 BDMA_CPAR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA

PA : Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a half-word address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address.
bits : 0 - 31 (32 bit)


BDMA_CM0AR5 (CM0AR5)

This register must not be written when the channel is enabled.
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDMA_CM0AR5 BDMA_CM0AR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA

MA : Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a half-word address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address.
bits : 0 - 31 (32 bit)


BDMA_CM1AR5 (CM1AR5)

BDMA channel x memory 1 address register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDMA_CM1AR5 BDMA_CM1AR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BDMA_CCR0 (CCR0)

DMA channel x configuration register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDMA_CCR0 BDMA_CCR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN TCIE HTIE TEIE DIR CIRC PINC MINC PSIZE MSIZE PL MEM2MEM DBM CT

EN : Channel enable This bit is set and cleared by software.
bits : 0 - 0 (1 bit)

TCIE : Transfer complete interrupt enable This bit is set and cleared by software.
bits : 1 - 1 (1 bit)

HTIE : Half transfer interrupt enable This bit is set and cleared by software.
bits : 2 - 2 (1 bit)

TEIE : Transfer error interrupt enable This bit is set and cleared by software.
bits : 3 - 3 (1 bit)

DIR : Data transfer direction This bit is set and cleared by software.
bits : 4 - 4 (1 bit)

CIRC : Circular mode This bit is set and cleared by software.
bits : 5 - 5 (1 bit)

PINC : Peripheral increment mode This bit is set and cleared by software.
bits : 6 - 6 (1 bit)

MINC : Memory increment mode This bit is set and cleared by software.
bits : 7 - 7 (1 bit)

PSIZE : Peripheral size These bits are set and cleared by software.
bits : 8 - 9 (2 bit)

MSIZE : Memory size These bits are set and cleared by software.
bits : 10 - 11 (2 bit)

PL : Channel priority level These bits are set and cleared by software.
bits : 12 - 13 (2 bit)

MEM2MEM : Memory to memory mode This bit is set and cleared by software.
bits : 14 - 14 (1 bit)

DBM : double-buffer mode
bits : 15 - 15 (1 bit)

CT : current target memory of DMA transfer in double-buffer mode
bits : 16 - 16 (1 bit)


BDMA_CCR6 (CCR6)

DMA channel x configuration register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDMA_CCR6 BDMA_CCR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN TCIE HTIE TEIE DIR CIRC PINC MINC PSIZE MSIZE PL MEM2MEM DBM CT

EN : Channel enable This bit is set and cleared by software.
bits : 0 - 0 (1 bit)

TCIE : Transfer complete interrupt enable This bit is set and cleared by software.
bits : 1 - 1 (1 bit)

HTIE : Half transfer interrupt enable This bit is set and cleared by software.
bits : 2 - 2 (1 bit)

TEIE : Transfer error interrupt enable This bit is set and cleared by software.
bits : 3 - 3 (1 bit)

DIR : Data transfer direction This bit is set and cleared by software.
bits : 4 - 4 (1 bit)

CIRC : Circular mode This bit is set and cleared by software.
bits : 5 - 5 (1 bit)

PINC : Peripheral increment mode This bit is set and cleared by software.
bits : 6 - 6 (1 bit)

MINC : Memory increment mode This bit is set and cleared by software.
bits : 7 - 7 (1 bit)

PSIZE : Peripheral size These bits are set and cleared by software.
bits : 8 - 9 (2 bit)

MSIZE : Memory size These bits are set and cleared by software.
bits : 10 - 11 (2 bit)

PL : Channel priority level These bits are set and cleared by software.
bits : 12 - 13 (2 bit)

MEM2MEM : Memory to memory mode This bit is set and cleared by software.
bits : 14 - 14 (1 bit)

DBM : double-buffer mode
bits : 15 - 15 (1 bit)

CT : current target memory of DMA transfer in double-buffer mode
bits : 16 - 16 (1 bit)


BDMA_CNDTR6 (CNDTR6)

DMA channel x number of data register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDMA_CNDTR6 BDMA_CNDTR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT

NDT : Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not.
bits : 0 - 15 (16 bit)


BDMA_CPAR6 (CPAR6)

This register must not be written when the channel is enabled.
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDMA_CPAR6 BDMA_CPAR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA

PA : Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a half-word address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address.
bits : 0 - 31 (32 bit)


BDMA_CM0AR6 (CM0AR6)

This register must not be written when the channel is enabled.
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDMA_CM0AR6 BDMA_CM0AR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA

MA : Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a half-word address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address.
bits : 0 - 31 (32 bit)


BDMA_CM1AR6 (CM1AR6)

BDMA channel x memory 1 address register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDMA_CM1AR6 BDMA_CM1AR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BDMA_CCR7 (CCR7)

DMA channel x configuration register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDMA_CCR7 BDMA_CCR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN TCIE HTIE TEIE DIR CIRC PINC MINC PSIZE MSIZE PL MEM2MEM DBM CT

EN : Channel enable This bit is set and cleared by software.
bits : 0 - 0 (1 bit)

TCIE : Transfer complete interrupt enable This bit is set and cleared by software.
bits : 1 - 1 (1 bit)

HTIE : Half transfer interrupt enable This bit is set and cleared by software.
bits : 2 - 2 (1 bit)

TEIE : Transfer error interrupt enable This bit is set and cleared by software.
bits : 3 - 3 (1 bit)

DIR : Data transfer direction This bit is set and cleared by software.
bits : 4 - 4 (1 bit)

CIRC : Circular mode This bit is set and cleared by software.
bits : 5 - 5 (1 bit)

PINC : Peripheral increment mode This bit is set and cleared by software.
bits : 6 - 6 (1 bit)

MINC : Memory increment mode This bit is set and cleared by software.
bits : 7 - 7 (1 bit)

PSIZE : Peripheral size These bits are set and cleared by software.
bits : 8 - 9 (2 bit)

MSIZE : Memory size These bits are set and cleared by software.
bits : 10 - 11 (2 bit)

PL : Channel priority level These bits are set and cleared by software.
bits : 12 - 13 (2 bit)

MEM2MEM : Memory to memory mode This bit is set and cleared by software.
bits : 14 - 14 (1 bit)

DBM : double-buffer mode
bits : 15 - 15 (1 bit)

CT : current target memory of DMA transfer in double-buffer mode
bits : 16 - 16 (1 bit)


BDMA_CNDTR7 (CNDTR7)

DMA channel x number of data register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDMA_CNDTR7 BDMA_CNDTR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT

NDT : Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not.
bits : 0 - 15 (16 bit)


BDMA_CPAR7 (CPAR7)

This register must not be written when the channel is enabled.
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDMA_CPAR7 BDMA_CPAR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA

PA : Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a half-word address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address.
bits : 0 - 31 (32 bit)


BDMA_CM0AR7 (CM0AR7)

This register must not be written when the channel is enabled.
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDMA_CM0AR7 BDMA_CM0AR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA

MA : Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a half-word address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address.
bits : 0 - 31 (32 bit)


BDMA_CM1AR7 (CM1AR7)

BDMA channel x memory 1 address register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDMA_CM1AR7 BDMA_CM1AR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BDMA_CNDTR0 (CNDTR0)

DMA channel x number of data register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDMA_CNDTR0 BDMA_CNDTR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT

NDT : Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not.
bits : 0 - 15 (16 bit)



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