\n

VREFBUF

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

VREFBUF_CSR (CSR)

VREFBUF_CCR (CCR)


VREFBUF_CSR (CSR)

VREFBUF control and status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VREFBUF_CSR VREFBUF_CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENVR HIZ VRR VRS

ENVR : Voltage reference buffer mode enable This bit is used to enable the voltage reference buffer mode.
bits : 0 - 0 (1 bit)
access : read-write

HIZ : High impedance mode This bit controls the analog switch to connect or not the VREF+ pin. Refer to Table196: VREF buffer modes for the mode descriptions depending on ENVR bit configuration.
bits : 1 - 1 (1 bit)
access : read-write

VRR : Voltage reference buffer ready
bits : 3 - 3 (1 bit)
access : read-only

VRS : Voltage reference scale These bits select the value generated by the voltage reference buffer. Other: Reserved
bits : 4 - 6 (3 bit)
access : read-write


VREFBUF_CCR (CCR)

VREFBUF calibration control register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VREFBUF_CCR VREFBUF_CCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRIM

TRIM : Trimming code These bits are automatically initialized after reset with the trimming value stored in the Flash memory during the production test. Writing into these bits allows to tune the internal reference buffer voltage.
bits : 0 - 5 (6 bit)



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.