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PWR

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

PWR_CR1 (CR1)

PWR_CPUCR (CPUCR)

PWR_D3CR (D3CR)

PWR_WKUPCR (WKUPCR)

PWR_WKUPFR (WKUPFR)

PWR_WKUPEPR (WKUPEPR)

PWR_CSR1 (CSR1)

PWR_CR2 (CR2)

PWR_CR3 (CR3)


PWR_CR1 (CR1)

PWR control register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWR_CR1 PWR_CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPDS PVDE PLS DBP FLPS SVOS AVDEN ALS

LPDS : Low-power Deepsleep with SVOS3 (SVOS4 and SVOS5 always use low-power, regardless of the setting of this bit)
bits : 0 - 0 (1 bit)

PVDE : Programmable voltage detector enable
bits : 4 - 4 (1 bit)

PLS : Programmable voltage detector level selection These bits select the voltage threshold detected by the PVD. Note: Refer to Section Electrical characteristics of the product datasheet for more details.
bits : 5 - 7 (3 bit)

DBP : Disable backup domain write protection In reset state, the RCC_BDCR register, the RTC registers (including the backup registers), BREN and MOEN bits in PWR_CR2 register, are protected against parasitic write access. This bit must be set to enable write access to these registers.
bits : 8 - 8 (1 bit)

FLPS : Flash low-power mode in DStop mode This bit allows to obtain the best trade-off between low-power consumption and restart time when exiting from DStop mode. When it is set, the Flash memory enters low-power mode when D1 domain is in DStop mode.
bits : 9 - 9 (1 bit)

SVOS : System Stop mode voltage scaling selection These bits control the VCORE voltage level in system Stop mode, to obtain the best trade-off between power consumption and performance.
bits : 14 - 15 (2 bit)

AVDEN : Peripheral voltage monitor on VDDA enable
bits : 16 - 16 (1 bit)

ALS : Analog voltage detector level selection These bits select the voltage threshold detected by the AVD.
bits : 17 - 18 (2 bit)


PWR_CPUCR (CPUCR)

This register allows controlling CPU1 power.
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWR_CPUCR PWR_CPUCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDDS_D1 PDDS_D2 PDDS_D3 HOLD2F STOPF SBF SBF_D1 SBF_D2 CSSF HOLD2 RUN_D3

PDDS_D1 : D1 domain Power Down Deepsleep selection. This bit allows CPU1 to define the Deepsleep mode for D1 domain.
bits : 0 - 0 (1 bit)
access : read-write

PDDS_D2 : D2 domain Power Down Deepsleep. This bit allows CPU1 to define the Deepsleep mode for D2 domain.
bits : 1 - 1 (1 bit)
access : read-write

PDDS_D3 : System D3 domain Power Down Deepsleep. This bit allows CPU1 to define the Deepsleep mode for System D3 domain.
bits : 2 - 2 (1 bit)
access : read-write

HOLD2F : CPU2 on hold wakeup flag
bits : 4 - 4 (1 bit)
access : read-only

STOPF : STOP flag This bit is set by hardware and cleared only by any reset or by setting the CPU1 CSSF bit.
bits : 5 - 5 (1 bit)
access : read-only

SBF : System Standby flag This bit is set by hardware and cleared only by a POR (Power-on Reset) or by setting the CPU1 CSSF bit
bits : 6 - 6 (1 bit)
access : read-only

SBF_D1 : D1 domain DStandby flag This bit is set by hardware and cleared by any system reset or by setting the CPU1 CSSF bit. Once set, this bit can be cleared only when the D1 domain is no longer in DStandby mode.
bits : 7 - 7 (1 bit)
access : read-only

SBF_D2 : D2 domain DStandby flag This bit is set by hardware and cleared by any system reset or by setting the CPU1 CSSF bit. Once set, this bit can be cleared only when the D2 domain is no longer in DStandby mode.
bits : 8 - 8 (1 bit)
access : read-only

CSSF : Clear D1 domain CPU1 Standby, Stop and HOLD flags (always read as 0) This bit is cleared to 0 by hardware.
bits : 9 - 9 (1 bit)
access : read-write

HOLD2 : Hold the CPU2 and allocated peripherals when exiting from Stop mode
bits : 10 - 10 (1 bit)
access : read-write

RUN_D3 : Keep system D3 domain in Run mode regardless of the CPU sub-systems modes
bits : 11 - 11 (1 bit)
access : read-write


PWR_D3CR (D3CR)

This register allows controlling D3 domain power.Following reset VOSRDY will be read 1 by software
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWR_D3CR PWR_D3CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VOSRDY VOS

VOSRDY : VOS Ready bit for VCORE voltage scaling output selection. This bit is set to 1 by hardware when Bypass mode is selected in PWR control register 3 (PWR_CR3).
bits : 13 - 13 (1 bit)
access : read-only

VOS : Voltage scaling selection according to performance These bits control the VCORE voltage level and allow to obtains the best trade-off between power consumption and performance: When increasing the performance, the voltage scaling shall be changed before increasing the system frequency. When decreasing performance, the system frequency shall first be decreased before changing the voltage scaling.
bits : 14 - 15 (2 bit)
access : read-write


PWR_WKUPCR (WKUPCR)

reset only by system reset, not reset by wakeup from Standby mode5 wait states are required when writing this register (when clearing a WKUPF bit in PWR_WKUPFR, the AHB write access will complete after the WKUPF has been cleared).
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWR_WKUPCR PWR_WKUPCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WKUPC

WKUPC : Clear Wakeup pin flag for WKUP. These bits are always read as 0.
bits : 0 - 5 (6 bit)


PWR_WKUPFR (WKUPFR)

reset only by system reset, not reset by wakeup from Standby mode
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PWR_WKUPFR PWR_WKUPFR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WKUPF1 WKUPF2 WKUPF3 WKUPF4 WKUPF5 WKUPF6

WKUPF1 : Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR).
bits : 0 - 0 (1 bit)

WKUPF2 : Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR).
bits : 1 - 1 (1 bit)

WKUPF3 : Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR).
bits : 2 - 2 (1 bit)

WKUPF4 : Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR).
bits : 3 - 3 (1 bit)

WKUPF5 : Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR).
bits : 4 - 4 (1 bit)

WKUPF6 : Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR).
bits : 5 - 5 (1 bit)


PWR_WKUPEPR (WKUPEPR)

Reset only by system reset, not reset by wakeup from Standby mode
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWR_WKUPEPR PWR_WKUPEPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WKUPEN1 WKUPEN2 WKUPEN3 WKUPEN4 WKUPEN5 WKUPEN6 WKUPP1 WKUPP2 WKUPP3 WKUPP4 WKUPP5 WKUPP6 WKUPPUPD1 WKUPPUPD2 WKUPPUPD3 WKUPPUPD4 WKUPPUPD5 WKUPPUPD6

WKUPEN1 : Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge.
bits : 0 - 0 (1 bit)

WKUPEN2 : Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge.
bits : 1 - 1 (1 bit)

WKUPEN3 : Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge.
bits : 2 - 2 (1 bit)

WKUPEN4 : Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge.
bits : 3 - 3 (1 bit)

WKUPEN5 : Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge.
bits : 4 - 4 (1 bit)

WKUPEN6 : Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge.
bits : 5 - 5 (1 bit)

WKUPP1 : Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin.
bits : 8 - 8 (1 bit)

WKUPP2 : Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin.
bits : 9 - 9 (1 bit)

WKUPP3 : Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin.
bits : 10 - 10 (1 bit)

WKUPP4 : Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin.
bits : 11 - 11 (1 bit)

WKUPP5 : Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin.
bits : 12 - 12 (1 bit)

WKUPP6 : Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin.
bits : 13 - 13 (1 bit)

WKUPPUPD1 : Wakeup pin pull configuration
bits : 16 - 17 (2 bit)

WKUPPUPD2 : Wakeup pin pull configuration
bits : 18 - 19 (2 bit)

WKUPPUPD3 : Wakeup pin pull configuration
bits : 20 - 21 (2 bit)

WKUPPUPD4 : Wakeup pin pull configuration
bits : 22 - 23 (2 bit)

WKUPPUPD5 : Wakeup pin pull configuration
bits : 24 - 25 (2 bit)

WKUPPUPD6 : Wakeup pin pull configuration for WKUP(truncate(n/2)-7) These bits define the I/O pad pull configuration used when WKUPEN(truncate(n/2)-7) = 1. The associated GPIO port pull configuration shall be set to the same value or to 00. The Wakeup pin pull configuration is kept in Standby mode.
bits : 26 - 27 (2 bit)


PWR_CSR1 (CSR1)

PWR control status register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PWR_CSR1 PWR_CSR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PVDO ACTVOSRDY ACTVOS AVDO

PVDO : Programmable voltage detect output This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the PVDE bit. Note: since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the PVDE bit is set.
bits : 4 - 4 (1 bit)

ACTVOSRDY : Voltage levels ready bit for currently used VOS and SDLEVEL This bit is set to 1 by hardware when the voltage regulator and the SD converter are both disabled and Bypass mode is selected in PWR control register 3 (PWR_CR3).
bits : 13 - 13 (1 bit)

ACTVOS : VOS currently applied for VCORE voltage scaling selection. These bits reflect the last VOS value applied to the PMU.
bits : 14 - 15 (2 bit)

AVDO : Analog voltage detector output on VDDA This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit. Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the AVDEN bit is set.
bits : 16 - 16 (1 bit)


PWR_CR2 (CR2)

This register is not reset by wakeup from Standby mode, RESET signal and VDD POR. It is only reset by VSW POR and VSWRST reset. This register shall not be accessed when VSWRST bit in RCC_BDCR register resets the VSW domain.After reset, PWR_CR2 register is write-protected. Prior to modifying its content, the DBP bit in PWR_CR1 register must be set to disable the write protection.
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWR_CR2 PWR_CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BREN MONEN BRRDY VBATL VBATH TEMPL TEMPH

BREN : Backup regulator enable When set, the Backup regulator (used to maintain the backup RAM content in Standby and VBAT modes) is enabled. If BREN is reset, the backup regulator is switched off. The backup RAM can still be used in Run and Stop modes. However, its content will be lost in Standby and VBAT modes. If BREN is set, the application must wait till the Backup Regulator Ready flag (BRRDY) is set to indicate that the data written into the SRAM will be maintained in Standby and VBAT modes.
bits : 0 - 0 (1 bit)
access : read-write

MONEN : VBAT and temperature monitoring enable When set, the VBAT supply and temperature monitoring is enabled.
bits : 4 - 4 (1 bit)
access : read-write

BRRDY : Backup regulator ready This bit is set by hardware to indicate that the Backup regulator is ready.
bits : 16 - 16 (1 bit)
access : read-only

VBATL : VBAT level monitoring versus low threshold
bits : 20 - 20 (1 bit)
access : read-only

VBATH : VBAT level monitoring versus high threshold
bits : 21 - 21 (1 bit)
access : read-only

TEMPL : Temperature level monitoring versus low threshold
bits : 22 - 22 (1 bit)
access : read-only

TEMPH : Temperature level monitoring versus high threshold
bits : 23 - 23 (1 bit)
access : read-only


PWR_CR3 (CR3)

Reset only by POR only, not reset by wakeup from Standby mode and RESET pad. The lower byte of this register is written once after POR and shall be written before changing VOS level or ck_sys clock frequency. No limitation applies to the upper bytes.Programming data corresponding to an invalid combination of SDLEVEL, SDEXTHP, SDEN, LDOEN and BYPASS bits (see Table9) will be ignored: data will not be written, the written-once mechanism will lock the register and any further write access will be ignored. The default supply configuration will be kept and the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1) will go on indicating invalid voltage levels. The system shall be power cycled before writing a new value.
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWR_CR3 PWR_CR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BYPASS LDOEN SDEN SDEXTHP SDLEVEL VBE VBRS SDEXTRDY USB33DEN USBREGEN USB33RDY

BYPASS : Power management unit bypass
bits : 0 - 0 (1 bit)
access : read-write

LDOEN : Low drop-out regulator enable
bits : 1 - 1 (1 bit)
access : read-write

SDEN : SD converter Enable
bits : 2 - 2 (1 bit)
access : read-write

SDEXTHP : Step-down converter forced ON and in High Power MR mode
bits : 3 - 3 (1 bit)
access : read-write

SDLEVEL : Step-down converter voltage output level selection
bits : 4 - 5 (2 bit)
access : read-write

VBE : VBAT charging enable
bits : 8 - 8 (1 bit)
access : read-write

VBRS : VBAT charging resistor selection
bits : 9 - 9 (1 bit)
access : read-write

SDEXTRDY : Step-down converter external supply ready
bits : 16 - 16 (1 bit)
access : read-only

USB33DEN : VDD33USB voltage level detector enable.
bits : 24 - 24 (1 bit)
access : read-write

USBREGEN : USB regulator enable.
bits : 25 - 25 (1 bit)
access : read-write

USB33RDY : USB supply ready.
bits : 26 - 26 (1 bit)
access : read-only



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