\n

DMAMUX

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

DMAMUX1_C0CR (C0CR)

DMAMUX1_C4CR (C4CR)

DMAMUX1_RG0CR (RG0CR)

DMAMUX1_RG1CR (RG1CR)

DMAMUX1_RG2CR (RG2CR)

DMAMUX1_RG3CR (RG3CR)

DMAMUX1_RG4CR (RG4CR)

DMAMUX1_RG5CR (RG5CR)

DMAMUX1_RG6CR (RG6CR)

DMAMUX1_RG7CR (RG7CR)

DMAMUX1_C5CR (C5CR)

DMAMUX1_RGSR (RGSR)

DMAMUX1_RGCFR (RGCFR)

DMAMUX1_C6CR (C6CR)

DMAMUX1_C7CR (C7CR)

DMAMUX1_C8CR (C8CR)

DMAMUX1_C9CR (C9CR)

DMAMUX1_C10CR (C10CR)

DMAMUX1_C11CR (C11CR)

DMAMUX1_C12CR (C12CR)

DMAMUX1_C13CR (C13CR)

DMAMUX1_C14CR (C14CR)

DMAMUX1_C15CR (C15CR)

DMAMUX1_C1CR (C1CR)

DMAMUX1_C2CR (C2CR)

DMAMUX1_CSR (CSR)

DMAMUX1_CFR (CFR)

DMAMUX1_C3CR (C3CR)


DMAMUX1_C0CR (C0CR)

DMAMux - DMA request line multiplexer channel x control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1_C0CR DMAMUX1_C0CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : Input DMA request line selected
bits : 0 - 7 (8 bit)

SOIE : Interrupt enable at synchronization event overrun
bits : 8 - 8 (1 bit)

EGE : Event generation enable/disable
bits : 9 - 9 (1 bit)

SE : Synchronous operating mode enable/disable
bits : 16 - 16 (1 bit)

SPOL : Synchronization event type selector Defines the synchronization event on the selected synchronization input:
bits : 17 - 18 (2 bit)

NBREQ : Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
bits : 19 - 23 (5 bit)

SYNC_ID : Synchronization input selected
bits : 24 - 28 (5 bit)


DMAMUX1_C4CR (C4CR)

DMAMux - DMA request line multiplexer channel x control register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1_C4CR DMAMUX1_C4CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : Input DMA request line selected
bits : 0 - 7 (8 bit)

SOIE : Interrupt enable at synchronization event overrun
bits : 8 - 8 (1 bit)

EGE : Event generation enable/disable
bits : 9 - 9 (1 bit)

SE : Synchronous operating mode enable/disable
bits : 16 - 16 (1 bit)

SPOL : Synchronization event type selector Defines the synchronization event on the selected synchronization input:
bits : 17 - 18 (2 bit)

NBREQ : Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
bits : 19 - 23 (5 bit)

SYNC_ID : Synchronization input selected
bits : 24 - 28 (5 bit)


DMAMUX1_RG0CR (RG0CR)

DMAMux - DMA request generator channel x control register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1_RG0CR DMAMUX1_RG0CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIG_ID OIE GE GPOL GNBREQ

SIG_ID : DMA request trigger input selected
bits : 0 - 4 (5 bit)

OIE : Interrupt enable at trigger event overrun
bits : 8 - 8 (1 bit)

GE : DMA request generator channel enable/disable
bits : 16 - 16 (1 bit)

GPOL : DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input
bits : 17 - 18 (2 bit)

GNBREQ : Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.
bits : 19 - 23 (5 bit)


DMAMUX1_RG1CR (RG1CR)

DMAMux - DMA request generator channel x control register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1_RG1CR DMAMUX1_RG1CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIG_ID OIE GE GPOL GNBREQ

SIG_ID : DMA request trigger input selected
bits : 0 - 4 (5 bit)

OIE : Interrupt enable at trigger event overrun
bits : 8 - 8 (1 bit)

GE : DMA request generator channel enable/disable
bits : 16 - 16 (1 bit)

GPOL : DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input
bits : 17 - 18 (2 bit)

GNBREQ : Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.
bits : 19 - 23 (5 bit)


DMAMUX1_RG2CR (RG2CR)

DMAMux - DMA request generator channel x control register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1_RG2CR DMAMUX1_RG2CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIG_ID OIE GE GPOL GNBREQ

SIG_ID : DMA request trigger input selected
bits : 0 - 4 (5 bit)

OIE : Interrupt enable at trigger event overrun
bits : 8 - 8 (1 bit)

GE : DMA request generator channel enable/disable
bits : 16 - 16 (1 bit)

GPOL : DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input
bits : 17 - 18 (2 bit)

GNBREQ : Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.
bits : 19 - 23 (5 bit)


DMAMUX1_RG3CR (RG3CR)

DMAMux - DMA request generator channel x control register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1_RG3CR DMAMUX1_RG3CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIG_ID OIE GE GPOL GNBREQ

SIG_ID : DMA request trigger input selected
bits : 0 - 4 (5 bit)

OIE : Interrupt enable at trigger event overrun
bits : 8 - 8 (1 bit)

GE : DMA request generator channel enable/disable
bits : 16 - 16 (1 bit)

GPOL : DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input
bits : 17 - 18 (2 bit)

GNBREQ : Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.
bits : 19 - 23 (5 bit)


DMAMUX1_RG4CR (RG4CR)

DMAMux - DMA request generator channel x control register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1_RG4CR DMAMUX1_RG4CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIG_ID OIE GE GPOL GNBREQ

SIG_ID : DMA request trigger input selected
bits : 0 - 4 (5 bit)

OIE : Interrupt enable at trigger event overrun
bits : 8 - 8 (1 bit)

GE : DMA request generator channel enable/disable
bits : 16 - 16 (1 bit)

GPOL : DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input
bits : 17 - 18 (2 bit)

GNBREQ : Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.
bits : 19 - 23 (5 bit)


DMAMUX1_RG5CR (RG5CR)

DMAMux - DMA request generator channel x control register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1_RG5CR DMAMUX1_RG5CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIG_ID OIE GE GPOL GNBREQ

SIG_ID : DMA request trigger input selected
bits : 0 - 4 (5 bit)

OIE : Interrupt enable at trigger event overrun
bits : 8 - 8 (1 bit)

GE : DMA request generator channel enable/disable
bits : 16 - 16 (1 bit)

GPOL : DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input
bits : 17 - 18 (2 bit)

GNBREQ : Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.
bits : 19 - 23 (5 bit)


DMAMUX1_RG6CR (RG6CR)

DMAMux - DMA request generator channel x control register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1_RG6CR DMAMUX1_RG6CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIG_ID OIE GE GPOL GNBREQ

SIG_ID : DMA request trigger input selected
bits : 0 - 4 (5 bit)

OIE : Interrupt enable at trigger event overrun
bits : 8 - 8 (1 bit)

GE : DMA request generator channel enable/disable
bits : 16 - 16 (1 bit)

GPOL : DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input
bits : 17 - 18 (2 bit)

GNBREQ : Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.
bits : 19 - 23 (5 bit)


DMAMUX1_RG7CR (RG7CR)

DMAMux - DMA request generator channel x control register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1_RG7CR DMAMUX1_RG7CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIG_ID OIE GE GPOL GNBREQ

SIG_ID : DMA request trigger input selected
bits : 0 - 4 (5 bit)

OIE : Interrupt enable at trigger event overrun
bits : 8 - 8 (1 bit)

GE : DMA request generator channel enable/disable
bits : 16 - 16 (1 bit)

GPOL : DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input
bits : 17 - 18 (2 bit)

GNBREQ : Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.
bits : 19 - 23 (5 bit)


DMAMUX1_C5CR (C5CR)

DMAMux - DMA request line multiplexer channel x control register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1_C5CR DMAMUX1_C5CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : Input DMA request line selected
bits : 0 - 7 (8 bit)

SOIE : Interrupt enable at synchronization event overrun
bits : 8 - 8 (1 bit)

EGE : Event generation enable/disable
bits : 9 - 9 (1 bit)

SE : Synchronous operating mode enable/disable
bits : 16 - 16 (1 bit)

SPOL : Synchronization event type selector Defines the synchronization event on the selected synchronization input:
bits : 17 - 18 (2 bit)

NBREQ : Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
bits : 19 - 23 (5 bit)

SYNC_ID : Synchronization input selected
bits : 24 - 28 (5 bit)


DMAMUX1_RGSR (RGSR)

DMAMux - DMA request generator status register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1_RGSR DMAMUX1_RGSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OF

OF : Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register.
bits : 0 - 7 (8 bit)


DMAMUX1_RGCFR (RGCFR)

DMAMux - DMA request generator clear flag register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1_RGCFR DMAMUX1_RGCFR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COF

COF : Clear trigger event overrun flag Upon setting, this bit clears the corresponding overrun flag OFx in the DMAMUX_RGCSR register.
bits : 0 - 7 (8 bit)


DMAMUX1_C6CR (C6CR)

DMAMux - DMA request line multiplexer channel x control register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1_C6CR DMAMUX1_C6CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : Input DMA request line selected
bits : 0 - 7 (8 bit)

SOIE : Interrupt enable at synchronization event overrun
bits : 8 - 8 (1 bit)

EGE : Event generation enable/disable
bits : 9 - 9 (1 bit)

SE : Synchronous operating mode enable/disable
bits : 16 - 16 (1 bit)

SPOL : Synchronization event type selector Defines the synchronization event on the selected synchronization input:
bits : 17 - 18 (2 bit)

NBREQ : Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
bits : 19 - 23 (5 bit)

SYNC_ID : Synchronization input selected
bits : 24 - 28 (5 bit)


DMAMUX1_C7CR (C7CR)

DMAMux - DMA request line multiplexer channel x control register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1_C7CR DMAMUX1_C7CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : Input DMA request line selected
bits : 0 - 7 (8 bit)

SOIE : Interrupt enable at synchronization event overrun
bits : 8 - 8 (1 bit)

EGE : Event generation enable/disable
bits : 9 - 9 (1 bit)

SE : Synchronous operating mode enable/disable
bits : 16 - 16 (1 bit)

SPOL : Synchronization event type selector Defines the synchronization event on the selected synchronization input:
bits : 17 - 18 (2 bit)

NBREQ : Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
bits : 19 - 23 (5 bit)

SYNC_ID : Synchronization input selected
bits : 24 - 28 (5 bit)


DMAMUX1_C8CR (C8CR)

DMAMux - DMA request line multiplexer channel x control register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1_C8CR DMAMUX1_C8CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : Input DMA request line selected
bits : 0 - 7 (8 bit)

SOIE : Interrupt enable at synchronization event overrun
bits : 8 - 8 (1 bit)

EGE : Event generation enable/disable
bits : 9 - 9 (1 bit)

SE : Synchronous operating mode enable/disable
bits : 16 - 16 (1 bit)

SPOL : Synchronization event type selector Defines the synchronization event on the selected synchronization input:
bits : 17 - 18 (2 bit)

NBREQ : Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
bits : 19 - 23 (5 bit)

SYNC_ID : Synchronization input selected
bits : 24 - 28 (5 bit)


DMAMUX1_C9CR (C9CR)

DMAMux - DMA request line multiplexer channel x control register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1_C9CR DMAMUX1_C9CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : Input DMA request line selected
bits : 0 - 7 (8 bit)

SOIE : Interrupt enable at synchronization event overrun
bits : 8 - 8 (1 bit)

EGE : Event generation enable/disable
bits : 9 - 9 (1 bit)

SE : Synchronous operating mode enable/disable
bits : 16 - 16 (1 bit)

SPOL : Synchronization event type selector Defines the synchronization event on the selected synchronization input:
bits : 17 - 18 (2 bit)

NBREQ : Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
bits : 19 - 23 (5 bit)

SYNC_ID : Synchronization input selected
bits : 24 - 28 (5 bit)


DMAMUX1_C10CR (C10CR)

DMAMux - DMA request line multiplexer channel x control register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1_C10CR DMAMUX1_C10CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : Input DMA request line selected
bits : 0 - 7 (8 bit)

SOIE : Interrupt enable at synchronization event overrun
bits : 8 - 8 (1 bit)

EGE : Event generation enable/disable
bits : 9 - 9 (1 bit)

SE : Synchronous operating mode enable/disable
bits : 16 - 16 (1 bit)

SPOL : Synchronization event type selector Defines the synchronization event on the selected synchronization input:
bits : 17 - 18 (2 bit)

NBREQ : Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
bits : 19 - 23 (5 bit)

SYNC_ID : Synchronization input selected
bits : 24 - 28 (5 bit)


DMAMUX1_C11CR (C11CR)

DMAMux - DMA request line multiplexer channel x control register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1_C11CR DMAMUX1_C11CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : Input DMA request line selected
bits : 0 - 7 (8 bit)

SOIE : Interrupt enable at synchronization event overrun
bits : 8 - 8 (1 bit)

EGE : Event generation enable/disable
bits : 9 - 9 (1 bit)

SE : Synchronous operating mode enable/disable
bits : 16 - 16 (1 bit)

SPOL : Synchronization event type selector Defines the synchronization event on the selected synchronization input:
bits : 17 - 18 (2 bit)

NBREQ : Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
bits : 19 - 23 (5 bit)

SYNC_ID : Synchronization input selected
bits : 24 - 28 (5 bit)


DMAMUX1_C12CR (C12CR)

DMAMux - DMA request line multiplexer channel x control register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1_C12CR DMAMUX1_C12CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : Input DMA request line selected
bits : 0 - 7 (8 bit)

SOIE : Interrupt enable at synchronization event overrun
bits : 8 - 8 (1 bit)

EGE : Event generation enable/disable
bits : 9 - 9 (1 bit)

SE : Synchronous operating mode enable/disable
bits : 16 - 16 (1 bit)

SPOL : Synchronization event type selector Defines the synchronization event on the selected synchronization input:
bits : 17 - 18 (2 bit)

NBREQ : Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
bits : 19 - 23 (5 bit)

SYNC_ID : Synchronization input selected
bits : 24 - 28 (5 bit)


DMAMUX1_C13CR (C13CR)

DMAMux - DMA request line multiplexer channel x control register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1_C13CR DMAMUX1_C13CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : Input DMA request line selected
bits : 0 - 7 (8 bit)

SOIE : Interrupt enable at synchronization event overrun
bits : 8 - 8 (1 bit)

EGE : Event generation enable/disable
bits : 9 - 9 (1 bit)

SE : Synchronous operating mode enable/disable
bits : 16 - 16 (1 bit)

SPOL : Synchronization event type selector Defines the synchronization event on the selected synchronization input:
bits : 17 - 18 (2 bit)

NBREQ : Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
bits : 19 - 23 (5 bit)

SYNC_ID : Synchronization input selected
bits : 24 - 28 (5 bit)


DMAMUX1_C14CR (C14CR)

DMAMux - DMA request line multiplexer channel x control register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1_C14CR DMAMUX1_C14CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : Input DMA request line selected
bits : 0 - 7 (8 bit)

SOIE : Interrupt enable at synchronization event overrun
bits : 8 - 8 (1 bit)

EGE : Event generation enable/disable
bits : 9 - 9 (1 bit)

SE : Synchronous operating mode enable/disable
bits : 16 - 16 (1 bit)

SPOL : Synchronization event type selector Defines the synchronization event on the selected synchronization input:
bits : 17 - 18 (2 bit)

NBREQ : Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
bits : 19 - 23 (5 bit)

SYNC_ID : Synchronization input selected
bits : 24 - 28 (5 bit)


DMAMUX1_C15CR (C15CR)

DMAMux - DMA request line multiplexer channel x control register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1_C15CR DMAMUX1_C15CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : Input DMA request line selected
bits : 0 - 7 (8 bit)

SOIE : Interrupt enable at synchronization event overrun
bits : 8 - 8 (1 bit)

EGE : Event generation enable/disable
bits : 9 - 9 (1 bit)

SE : Synchronous operating mode enable/disable
bits : 16 - 16 (1 bit)

SPOL : Synchronization event type selector Defines the synchronization event on the selected synchronization input:
bits : 17 - 18 (2 bit)

NBREQ : Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
bits : 19 - 23 (5 bit)

SYNC_ID : Synchronization input selected
bits : 24 - 28 (5 bit)


DMAMUX1_C1CR (C1CR)

DMAMux - DMA request line multiplexer channel x control register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1_C1CR DMAMUX1_C1CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : Input DMA request line selected
bits : 0 - 7 (8 bit)

SOIE : Interrupt enable at synchronization event overrun
bits : 8 - 8 (1 bit)

EGE : Event generation enable/disable
bits : 9 - 9 (1 bit)

SE : Synchronous operating mode enable/disable
bits : 16 - 16 (1 bit)

SPOL : Synchronization event type selector Defines the synchronization event on the selected synchronization input:
bits : 17 - 18 (2 bit)

NBREQ : Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
bits : 19 - 23 (5 bit)

SYNC_ID : Synchronization input selected
bits : 24 - 28 (5 bit)


DMAMUX1_C2CR (C2CR)

DMAMux - DMA request line multiplexer channel x control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1_C2CR DMAMUX1_C2CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : Input DMA request line selected
bits : 0 - 7 (8 bit)

SOIE : Interrupt enable at synchronization event overrun
bits : 8 - 8 (1 bit)

EGE : Event generation enable/disable
bits : 9 - 9 (1 bit)

SE : Synchronous operating mode enable/disable
bits : 16 - 16 (1 bit)

SPOL : Synchronization event type selector Defines the synchronization event on the selected synchronization input:
bits : 17 - 18 (2 bit)

NBREQ : Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
bits : 19 - 23 (5 bit)

SYNC_ID : Synchronization input selected
bits : 24 - 28 (5 bit)


DMAMUX1_CSR (CSR)

DMAMUX request line multiplexer interrupt channel status register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1_CSR DMAMUX1_CSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOF

SOF : Synchronization overrun event flag
bits : 0 - 15 (16 bit)


DMAMUX1_CFR (CFR)

DMAMUX request line multiplexer interrupt clear flag register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1_CFR DMAMUX1_CFR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSOF

CSOF : Clear synchronization overrun event flag
bits : 0 - 15 (16 bit)


DMAMUX1_C3CR (C3CR)

DMAMux - DMA request line multiplexer channel x control register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1_C3CR DMAMUX1_C3CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : Input DMA request line selected
bits : 0 - 7 (8 bit)

SOIE : Interrupt enable at synchronization event overrun
bits : 8 - 8 (1 bit)

EGE : Event generation enable/disable
bits : 9 - 9 (1 bit)

SE : Synchronous operating mode enable/disable
bits : 16 - 16 (1 bit)

SPOL : Synchronization event type selector Defines the synchronization event on the selected synchronization input:
bits : 17 - 18 (2 bit)

NBREQ : Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
bits : 19 - 23 (5 bit)

SYNC_ID : Synchronization input selected
bits : 24 - 28 (5 bit)



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.