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USART

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR1

GTPR

RTOR

RQR

ISR

ICR

RDR

TDR

PRESC

CR2

CR3

BRR


CR1

Control register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR1 CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UE UESM RE TE IDLEIE RXNEIE TCIE TXEIE PEIE PS PCE WAKE M0 MME CMIE OVER8 DEDT0 DEDT1 DEDT2 DEDT3 DEDT4 DEAT0 DEAT1 DEAT2 DEAT3 DEAT4 RTOIE EOBIE M1 FIFOEN TXFEIE RXFFIE

UE : USART enable
bits : 0 - 0 (1 bit)

UESM : USART enable in Stop mode
bits : 1 - 1 (1 bit)

RE : Receiver enable
bits : 2 - 2 (1 bit)

TE : Transmitter enable
bits : 3 - 3 (1 bit)

IDLEIE : IDLE interrupt enable
bits : 4 - 4 (1 bit)

RXNEIE : RXNE interrupt enable
bits : 5 - 5 (1 bit)

TCIE : Transmission complete interrupt enable
bits : 6 - 6 (1 bit)

TXEIE : interrupt enable
bits : 7 - 7 (1 bit)

PEIE : PE interrupt enable
bits : 8 - 8 (1 bit)

PS : Parity selection
bits : 9 - 9 (1 bit)

PCE : Parity control enable
bits : 10 - 10 (1 bit)

WAKE : Receiver wakeup method
bits : 11 - 11 (1 bit)

M0 : Word length
bits : 12 - 12 (1 bit)

MME : Mute mode enable
bits : 13 - 13 (1 bit)

CMIE : Character match interrupt enable
bits : 14 - 14 (1 bit)

OVER8 : Oversampling mode
bits : 15 - 15 (1 bit)

DEDT0 : DEDT0
bits : 16 - 16 (1 bit)

DEDT1 : DEDT1
bits : 17 - 17 (1 bit)

DEDT2 : DEDT2
bits : 18 - 18 (1 bit)

DEDT3 : DEDT3
bits : 19 - 19 (1 bit)

DEDT4 : Driver Enable de-assertion time
bits : 20 - 20 (1 bit)

DEAT0 : DEAT0
bits : 21 - 21 (1 bit)

DEAT1 : DEAT1
bits : 22 - 22 (1 bit)

DEAT2 : DEAT2
bits : 23 - 23 (1 bit)

DEAT3 : DEAT3
bits : 24 - 24 (1 bit)

DEAT4 : Driver Enable assertion time
bits : 25 - 25 (1 bit)

RTOIE : Receiver timeout interrupt enable
bits : 26 - 26 (1 bit)

EOBIE : End of Block interrupt enable
bits : 27 - 27 (1 bit)

M1 : Word length
bits : 28 - 28 (1 bit)

FIFOEN : FIFO mode enable
bits : 29 - 29 (1 bit)

TXFEIE : TXFIFO empty interrupt enable
bits : 30 - 30 (1 bit)

RXFFIE : RXFIFO Full interrupt enable
bits : 31 - 31 (1 bit)


GTPR

Guard time and prescaler register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GTPR GTPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PSC GT

PSC : Prescaler value
bits : 0 - 7 (8 bit)

GT : Guard time value
bits : 8 - 15 (8 bit)


RTOR

Receiver timeout register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTOR RTOR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RTO BLEN

RTO : Receiver timeout value
bits : 0 - 23 (24 bit)

BLEN : Block Length
bits : 24 - 31 (8 bit)


RQR

Request register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

RQR RQR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ABRRQ SBKRQ MMRQ RXFRQ TXFRQ

ABRRQ : Auto baud rate request
bits : 0 - 0 (1 bit)

SBKRQ : Send break request
bits : 1 - 1 (1 bit)

MMRQ : Mute mode request
bits : 2 - 2 (1 bit)

RXFRQ : Receive data flush request
bits : 3 - 3 (1 bit)

TXFRQ : Transmit data flush request
bits : 4 - 4 (1 bit)


ISR

Interrupt and status register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PE FE NF ORE IDLE RXNE TC TXE LBDF CTSIF CTS RTOF EOBF UDR ABRE ABRF BUSY CMF SBKF RWU WUF TEACK REACK TXFE RXFF TCBGT RXFT TXFT

PE : PE
bits : 0 - 0 (1 bit)

FE : FE
bits : 1 - 1 (1 bit)

NF : NF
bits : 2 - 2 (1 bit)

ORE : ORE
bits : 3 - 3 (1 bit)

IDLE : IDLE
bits : 4 - 4 (1 bit)

RXNE : RXNE
bits : 5 - 5 (1 bit)

TC : TC
bits : 6 - 6 (1 bit)

TXE : TXE
bits : 7 - 7 (1 bit)

LBDF : LBDF
bits : 8 - 8 (1 bit)

CTSIF : CTSIF
bits : 9 - 9 (1 bit)

CTS : CTS
bits : 10 - 10 (1 bit)

RTOF : RTOF
bits : 11 - 11 (1 bit)

EOBF : EOBF
bits : 12 - 12 (1 bit)

UDR : SPI slave underrun error flag
bits : 13 - 13 (1 bit)

ABRE : ABRE
bits : 14 - 14 (1 bit)

ABRF : ABRF
bits : 15 - 15 (1 bit)

BUSY : BUSY
bits : 16 - 16 (1 bit)

CMF : CMF
bits : 17 - 17 (1 bit)

SBKF : SBKF
bits : 18 - 18 (1 bit)

RWU : RWU
bits : 19 - 19 (1 bit)

WUF : WUF
bits : 20 - 20 (1 bit)

TEACK : TEACK
bits : 21 - 21 (1 bit)

REACK : REACK
bits : 22 - 22 (1 bit)

TXFE : TXFIFO Empty
bits : 23 - 23 (1 bit)

RXFF : RXFIFO Full
bits : 24 - 24 (1 bit)

TCBGT : Transmission complete before guard time flag
bits : 25 - 25 (1 bit)

RXFT : RXFIFO threshold flag
bits : 26 - 26 (1 bit)

TXFT : TXFIFO threshold flag
bits : 27 - 27 (1 bit)


ICR

Interrupt flag clear register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ICR ICR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PECF FECF NCF ORECF IDLECF TXFECF TCCF TCBGTC LBDCF CTSCF RTOCF EOBCF UDRCF CMCF WUCF

PECF : Parity error clear flag
bits : 0 - 0 (1 bit)

FECF : Framing error clear flag
bits : 1 - 1 (1 bit)

NCF : Noise detected clear flag
bits : 2 - 2 (1 bit)

ORECF : Overrun error clear flag
bits : 3 - 3 (1 bit)

IDLECF : Idle line detected clear flag
bits : 4 - 4 (1 bit)

TXFECF : TXFIFO empty clear flag
bits : 5 - 5 (1 bit)

TCCF : Transmission complete clear flag
bits : 6 - 6 (1 bit)

TCBGTC : Transmission complete before Guard time clear flag
bits : 7 - 7 (1 bit)

LBDCF : LIN break detection clear flag
bits : 8 - 8 (1 bit)

CTSCF : CTS clear flag
bits : 9 - 9 (1 bit)

RTOCF : Receiver timeout clear flag
bits : 11 - 11 (1 bit)

EOBCF : End of block clear flag
bits : 12 - 12 (1 bit)

UDRCF : SPI slave underrun clear flag
bits : 13 - 13 (1 bit)

CMCF : Character match clear flag
bits : 17 - 17 (1 bit)

WUCF : Wakeup from Stop mode clear flag
bits : 20 - 20 (1 bit)


RDR

Receive data register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RDR RDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDR

RDR : Receive data value
bits : 0 - 8 (9 bit)


TDR

Transmit data register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TDR TDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TDR

TDR : Transmit data value
bits : 0 - 8 (9 bit)


PRESC

USART prescaler register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRESC PRESC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRESCALER

PRESCALER : Clock prescaler
bits : 0 - 3 (4 bit)


CR2

Control register 2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR2 CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLVEN DIS_NSS ADDM7 LBDL LBDIE LBCL CPHA CPOL CLKEN STOP LINEN SWAP RXINV TXINV TAINV MSBFIRST ABREN ABRMOD0 ABRMOD1 RTOEN ADD0_3 ADD4_7

SLVEN : Synchronous Slave mode enable
bits : 0 - 0 (1 bit)

DIS_NSS : When the DSI_NSS bit is set, the NSS pin input is ignored
bits : 3 - 3 (1 bit)

ADDM7 : 7-bit Address Detection/4-bit Address Detection
bits : 4 - 4 (1 bit)

LBDL : LIN break detection length
bits : 5 - 5 (1 bit)

LBDIE : LIN break detection interrupt enable
bits : 6 - 6 (1 bit)

LBCL : Last bit clock pulse
bits : 8 - 8 (1 bit)

CPHA : Clock phase
bits : 9 - 9 (1 bit)

CPOL : Clock polarity
bits : 10 - 10 (1 bit)

CLKEN : Clock enable
bits : 11 - 11 (1 bit)

STOP : STOP bits
bits : 12 - 13 (2 bit)

LINEN : LIN mode enable
bits : 14 - 14 (1 bit)

SWAP : Swap TX/RX pins
bits : 15 - 15 (1 bit)

RXINV : RX pin active level inversion
bits : 16 - 16 (1 bit)

TXINV : TX pin active level inversion
bits : 17 - 17 (1 bit)

TAINV : Binary data inversion
bits : 18 - 18 (1 bit)

MSBFIRST : Most significant bit first
bits : 19 - 19 (1 bit)

ABREN : Auto baud rate enable
bits : 20 - 20 (1 bit)

ABRMOD0 : ABRMOD0
bits : 21 - 21 (1 bit)

ABRMOD1 : Auto baud rate mode
bits : 22 - 22 (1 bit)

RTOEN : Receiver timeout enable
bits : 23 - 23 (1 bit)

ADD0_3 : Address of the USART node
bits : 24 - 27 (4 bit)

ADD4_7 : Address of the USART node
bits : 28 - 31 (4 bit)


CR3

Control register 3
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR3 CR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EIE IREN IRLP HDSEL NACK SCEN DMAR DMAT RTSE CTSE CTSIE ONEBIT OVRDIS DDRE DEM DEP SCARCNT WUS WUFIE TXFTIE TCBGTIE RXFTCFG RXFTIE TXFTCFG

EIE : Error interrupt enable
bits : 0 - 0 (1 bit)

IREN : Ir mode enable
bits : 1 - 1 (1 bit)

IRLP : Ir low-power
bits : 2 - 2 (1 bit)

HDSEL : Half-duplex selection
bits : 3 - 3 (1 bit)

NACK : Smartcard NACK enable
bits : 4 - 4 (1 bit)

SCEN : Smartcard mode enable
bits : 5 - 5 (1 bit)

DMAR : DMA enable receiver
bits : 6 - 6 (1 bit)

DMAT : DMA enable transmitter
bits : 7 - 7 (1 bit)

RTSE : RTS enable
bits : 8 - 8 (1 bit)

CTSE : CTS enable
bits : 9 - 9 (1 bit)

CTSIE : CTS interrupt enable
bits : 10 - 10 (1 bit)

ONEBIT : One sample bit method enable
bits : 11 - 11 (1 bit)

OVRDIS : Overrun Disable
bits : 12 - 12 (1 bit)

DDRE : DMA Disable on Reception Error
bits : 13 - 13 (1 bit)

DEM : Driver enable mode
bits : 14 - 14 (1 bit)

DEP : Driver enable polarity selection
bits : 15 - 15 (1 bit)

SCARCNT : Smartcard auto-retry count
bits : 17 - 19 (3 bit)

WUS : Wakeup from Stop mode interrupt flag selection
bits : 20 - 21 (2 bit)

WUFIE : Wakeup from Stop mode interrupt enable
bits : 22 - 22 (1 bit)

TXFTIE : TXFIFO threshold interrupt enable
bits : 23 - 23 (1 bit)

TCBGTIE : Transmission Complete before guard time, interrupt enable
bits : 24 - 24 (1 bit)

RXFTCFG : Receive FIFO threshold configuration
bits : 25 - 27 (3 bit)

RXFTIE : RXFIFO threshold interrupt enable
bits : 28 - 28 (1 bit)

TXFTCFG : TXFIFO threshold configuration
bits : 29 - 31 (3 bit)


BRR

Baud rate register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BRR BRR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BRR_0_3 BRR_4_15

BRR_0_3 : DIV_Fraction
bits : 0 - 3 (4 bit)

BRR_4_15 : DIV_Mantissa
bits : 4 - 15 (12 bit)



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