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Ethernet

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

MACCR

MACHT0R

DMAMR

DMASBMR

DMAISR

DMADSR

MACVR

DMACCR

DMACTxCR

DMACRxCR

DMACTxDLAR

DMACRxDLAR

DMACTxDTPR

DMACRxDTPR

DMACTxRLR

DMACRxRLR

DMACIER

DMACRxIWTR

MACDR

DMACCATxDR

DMACCARxDR

DMACCATxBR

DMACCARxBR

DMACSR

DMACMFCR

MACHWF1R

MACHWF2R

MACHT1R

MACMDIOAR

MACMDIODR

MACA0HR

MACA0LR

MACA1HR

MACA1LR

MACA2HR

MACA2LR

MACA3HR

MACA3LR

MACECR

MACVTR

MACVHTR

MACVIR

MACIVIR

MACQTxFCR

MMC_CONTROL

MMC_RX_INTERRUPT

MMC_TX_INTERRUPT

MMC_RX_INTERRUPT_MASK

MMC_TX_INTERRUPT_MASK

TX_SINGLE_COLLISION_GOOD_PACKETS (TX_SINGLE_COLLISION_GOOD_PACKETS)

TX_MULTIPLE_COLLISION_GOOD_PACKETS (TX_MULTIPLE_COLLISION_GOOD_PACKETS)

TX_PACKET_COUNT_GOOD

RX_CRC_ERROR_PACKETS

RX_ALIGNMENT_ERROR_PACKETS

RX_UNICAST_PACKETS_GOOD

TX_LPI_USEC_CNTR

TX_LPI_TRAN_CNTR

RX_LPI_USEC_CNTR

RX_LPI_TRAN_CNTR

MACPFR

MACRxFCR

MACL3L4C0R

MACL4A0R

MACL3A00R

MACL3A10R

MACL3A20

MACL3A30

MACL3L4C1R

MACL4A1R

MACL3A01R

MACL3A11R

MACL3A21R

MACL3A31R

MACARPAR

MACISR

MACTSCR

MACSSIR

MACSTSR

MACSTNR

MACSTSUR

MACSTNUR

MACTSAR

MACTSSR

MACTxTSSNR

MACTxTSSSR

MACIER

MACACR

MACATSNR

MACATSSR

MACTSIACR

MACTSEACR

MACTSICNR

MACTSECNR

MACPPSCR

MACRxTxSR

MACPPSTTSR

MACPPSTTNR

MACPPSIR

MACPPSWR

MACPOCR

MACSPI0R

MACSPI1R

MACSPI2R

MACLMIR

MACWTR

MACPCSR

MTLOMR

MTLISR

MACRWKPFR

MACLCSR

MTLTxQOMR

MTLTxQUR

MTLTxQDR

MTLQICSR

MTLRxQOMR

MTLRxQMPOCR

MTLRxQDR

MACLTCR

MACLETR

MAC1USTCR


MACCR

Operating mode configuration register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACCR MACCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RE TE PRELEN DC BL DR DCRS DO ECRSFD LM DM FES JE JD WD ACS CST S2KP GPSLCE IPG IPC SARC ARPEN

RE : Receiver Enable
bits : 0 - 0 (1 bit)

TE : TE
bits : 1 - 1 (1 bit)

PRELEN : PRELEN
bits : 2 - 3 (2 bit)

DC : DC
bits : 4 - 4 (1 bit)

BL : BL
bits : 5 - 6 (2 bit)

DR : DR
bits : 8 - 8 (1 bit)

DCRS : DCRS
bits : 9 - 9 (1 bit)

DO : DO
bits : 10 - 10 (1 bit)

ECRSFD : ECRSFD
bits : 11 - 11 (1 bit)

LM : LM
bits : 12 - 12 (1 bit)

DM : DM
bits : 13 - 13 (1 bit)

FES : FES
bits : 14 - 14 (1 bit)

JE : JE
bits : 16 - 16 (1 bit)

JD : JD
bits : 17 - 17 (1 bit)

WD : WD
bits : 19 - 19 (1 bit)

ACS : ACS
bits : 20 - 20 (1 bit)

CST : CST
bits : 21 - 21 (1 bit)

S2KP : S2KP
bits : 22 - 22 (1 bit)

GPSLCE : GPSLCE
bits : 23 - 23 (1 bit)

IPG : IPG
bits : 24 - 26 (3 bit)

IPC : IPC
bits : 27 - 27 (1 bit)

SARC : SARC
bits : 28 - 30 (3 bit)

ARPEN : ARPEN
bits : 31 - 31 (1 bit)


MACHT0R

Hash Table 0 register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACHT0R MACHT0R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HT31T0

HT31T0 : HT31T0
bits : 0 - 31 (32 bit)


DMAMR

DMA mode register
address_offset : 0x1000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMR DMAMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWR DA TXPR PR INTM

SWR : Software Reset
bits : 0 - 0 (1 bit)
access : read-write

DA : DMA Tx or Rx Arbitration Scheme
bits : 1 - 1 (1 bit)
access : read-only

TXPR : Transmit priority
bits : 11 - 11 (1 bit)
access : read-only

PR : Priority ratio
bits : 12 - 14 (3 bit)
access : read-only

INTM : Interrupt Mode
bits : 16 - 16 (1 bit)
access : read-write


DMASBMR

System bus mode register
address_offset : 0x1004 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMASBMR DMASBMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FB AAL MB RB

FB : Fixed Burst Length
bits : 0 - 0 (1 bit)
access : read-write

AAL : Address-Aligned Beats
bits : 12 - 12 (1 bit)
access : read-write

MB : Mixed Burst
bits : 14 - 14 (1 bit)
access : read-only

RB : Rebuild INCRx Burst
bits : 15 - 15 (1 bit)
access : read-only


DMAISR

Interrupt status register
address_offset : 0x1008 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DMAISR DMAISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DC0IS MTLIS MACIS

DC0IS : DMA Channel Interrupt Status
bits : 0 - 0 (1 bit)

MTLIS : MTL Interrupt Status
bits : 16 - 16 (1 bit)

MACIS : MAC Interrupt Status
bits : 17 - 17 (1 bit)


DMADSR

Debug status register
address_offset : 0x100C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DMADSR DMADSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AXWHSTS RPS0 TPS0

AXWHSTS : AHB Master Write Channel
bits : 0 - 0 (1 bit)

RPS0 : DMA Channel Receive Process State
bits : 8 - 11 (4 bit)

TPS0 : DMA Channel Transmit Process State
bits : 12 - 15 (4 bit)


MACVR

Version register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MACVR MACVR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SNPSVER USERVER

SNPSVER : SNPSVER
bits : 0 - 7 (8 bit)

USERVER : USERVER
bits : 8 - 15 (8 bit)


DMACCR

Channel control register
address_offset : 0x1100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACCR DMACCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSS PBLX8 DSL

MSS : Maximum Segment Size
bits : 0 - 13 (14 bit)

PBLX8 : 8xPBL mode
bits : 16 - 16 (1 bit)

DSL : Descriptor Skip Length
bits : 18 - 20 (3 bit)


DMACTxCR

Channel transmit control register
address_offset : 0x1104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACTxCR DMACTxCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ST OSF TSE TXPBL

ST : Start or Stop Transmission Command
bits : 0 - 0 (1 bit)

OSF : Operate on Second Packet
bits : 4 - 4 (1 bit)

TSE : TCP Segmentation Enabled
bits : 12 - 12 (1 bit)

TXPBL : Transmit Programmable Burst Length
bits : 16 - 21 (6 bit)


DMACRxCR

Channel receive control register
address_offset : 0x1108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACRxCR DMACRxCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SR RBSZ RXPBL RPF

SR : Start or Stop Receive Command
bits : 0 - 0 (1 bit)

RBSZ : Receive Buffer size
bits : 1 - 14 (14 bit)

RXPBL : RXPBL
bits : 16 - 21 (6 bit)

RPF : DMA Rx Channel Packet Flush
bits : 31 - 31 (1 bit)


DMACTxDLAR

Channel Tx descriptor list address register
address_offset : 0x1114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACTxDLAR DMACTxDLAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TDESLA

TDESLA : Start of Transmit List
bits : 2 - 31 (30 bit)


DMACRxDLAR

Channel Rx descriptor list address register
address_offset : 0x111C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACRxDLAR DMACRxDLAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDESLA

RDESLA : Start of Receive List
bits : 2 - 31 (30 bit)


DMACTxDTPR

Channel Tx descriptor tail pointer register
address_offset : 0x1120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACTxDTPR DMACTxDTPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TDT

TDT : Transmit Descriptor Tail Pointer
bits : 2 - 31 (30 bit)


DMACRxDTPR

Channel Rx descriptor tail pointer register
address_offset : 0x1128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACRxDTPR DMACRxDTPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDT

RDT : Receive Descriptor Tail Pointer
bits : 2 - 31 (30 bit)


DMACTxRLR

Channel Tx descriptor ring length register
address_offset : 0x112C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACTxRLR DMACTxRLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TDRL

TDRL : Transmit Descriptor Ring Length
bits : 0 - 9 (10 bit)


DMACRxRLR

Channel Rx descriptor ring length register
address_offset : 0x1130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACRxRLR DMACRxRLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDRL

RDRL : Receive Descriptor Ring Length
bits : 0 - 9 (10 bit)


DMACIER

Channel interrupt enable register
address_offset : 0x1134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACIER DMACIER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIE TXSE TBUE RIE RBUE RSE RWTE ETIE ERIE FBEE CDEE AIE NIE

TIE : Transmit Interrupt Enable
bits : 0 - 0 (1 bit)

TXSE : Transmit Stopped Enable
bits : 1 - 1 (1 bit)

TBUE : Transmit Buffer Unavailable Enable
bits : 2 - 2 (1 bit)

RIE : Receive Interrupt Enable
bits : 6 - 6 (1 bit)

RBUE : Receive Buffer Unavailable Enable
bits : 7 - 7 (1 bit)

RSE : Receive Stopped Enable
bits : 8 - 8 (1 bit)

RWTE : Receive Watchdog Timeout Enable
bits : 9 - 9 (1 bit)

ETIE : Early Transmit Interrupt Enable
bits : 10 - 10 (1 bit)

ERIE : Early Receive Interrupt Enable
bits : 11 - 11 (1 bit)

FBEE : Fatal Bus Error Enable
bits : 12 - 12 (1 bit)

CDEE : Context Descriptor Error Enable
bits : 13 - 13 (1 bit)

AIE : Abnormal Interrupt Summary Enable
bits : 14 - 14 (1 bit)

NIE : Normal Interrupt Summary Enable
bits : 15 - 15 (1 bit)


DMACRxIWTR

Channel Rx interrupt watchdog timer register
address_offset : 0x1138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACRxIWTR DMACRxIWTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RWT

RWT : Receive Interrupt Watchdog Timer Count
bits : 0 - 7 (8 bit)


MACDR

Debug register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MACDR MACDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RPESTS RFCFCSTS TPESTS TFCSTS

RPESTS : RPESTS
bits : 0 - 0 (1 bit)

RFCFCSTS : RFCFCSTS
bits : 1 - 2 (2 bit)

TPESTS : TPESTS
bits : 16 - 16 (1 bit)

TFCSTS : TFCSTS
bits : 17 - 18 (2 bit)


DMACCATxDR

Channel current application transmit descriptor register
address_offset : 0x1144 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DMACCATxDR DMACCATxDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CURTDESAPTR

CURTDESAPTR : Application Transmit Descriptor Address Pointer
bits : 0 - 31 (32 bit)


DMACCARxDR

Channel current application receive descriptor register
address_offset : 0x114C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DMACCARxDR DMACCARxDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CURRDESAPTR

CURRDESAPTR : Application Receive Descriptor Address Pointer
bits : 0 - 31 (32 bit)


DMACCATxBR

Channel current application transmit buffer register
address_offset : 0x1154 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DMACCATxBR DMACCATxBR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CURTBUFAPTR

CURTBUFAPTR : Application Transmit Buffer Address Pointer
bits : 0 - 31 (32 bit)


DMACCARxBR

Channel current application receive buffer register
address_offset : 0x115C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DMACCARxBR DMACCARxBR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CURRBUFAPTR

CURRBUFAPTR : Application Receive Buffer Address Pointer
bits : 0 - 31 (32 bit)


DMACSR

Channel status register
address_offset : 0x1160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACSR DMACSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TI TPS TBU RI RBU RPS RWT ET ER FBE CDE AIS NIS TEB REB

TI : Transmit Interrupt
bits : 0 - 0 (1 bit)
access : read-write

TPS : Transmit Process Stopped
bits : 1 - 1 (1 bit)
access : read-write

TBU : Transmit Buffer Unavailable
bits : 2 - 2 (1 bit)
access : read-write

RI : Receive Interrupt
bits : 6 - 6 (1 bit)
access : read-write

RBU : Receive Buffer Unavailable
bits : 7 - 7 (1 bit)
access : read-write

RPS : Receive Process Stopped
bits : 8 - 8 (1 bit)
access : read-write

RWT : Receive Watchdog Timeout
bits : 9 - 9 (1 bit)
access : read-write

ET : Early Transmit Interrupt
bits : 10 - 10 (1 bit)
access : read-write

ER : Early Receive Interrupt
bits : 11 - 11 (1 bit)
access : read-write

FBE : Fatal Bus Error
bits : 12 - 12 (1 bit)
access : read-write

CDE : Context Descriptor Error
bits : 13 - 13 (1 bit)
access : read-write

AIS : Abnormal Interrupt Summary
bits : 14 - 14 (1 bit)
access : read-write

NIS : Normal Interrupt Summary
bits : 15 - 15 (1 bit)
access : read-write

TEB : Tx DMA Error Bits
bits : 16 - 18 (3 bit)
access : read-only

REB : Rx DMA Error Bits
bits : 19 - 21 (3 bit)
access : read-only


DMACMFCR

Channel missed frame count register
address_offset : 0x116C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DMACMFCR DMACMFCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFC MFCO

MFC : Dropped Packet Counters
bits : 0 - 10 (11 bit)

MFCO : Overflow status of the MFC Counter
bits : 15 - 15 (1 bit)


MACHWF1R

HW feature 1 register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MACHWF1R MACHWF1R read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXFIFOSIZE TXFIFOSIZE OSTEN PTOEN ADVTHWORD DCBEN SPHEN TSOEN DBGMEMA AVSEL HASHTBLSZ L3L4FNUM

RXFIFOSIZE : RXFIFOSIZE
bits : 0 - 4 (5 bit)

TXFIFOSIZE : TXFIFOSIZE
bits : 6 - 10 (5 bit)

OSTEN : OSTEN
bits : 11 - 11 (1 bit)

PTOEN : PTOEN
bits : 12 - 12 (1 bit)

ADVTHWORD : ADVTHWORD
bits : 13 - 13 (1 bit)

DCBEN : DCBEN
bits : 16 - 16 (1 bit)

SPHEN : SPHEN
bits : 17 - 17 (1 bit)

TSOEN : TSOEN
bits : 18 - 18 (1 bit)

DBGMEMA : DBGMEMA
bits : 19 - 19 (1 bit)

AVSEL : AVSEL
bits : 20 - 20 (1 bit)

HASHTBLSZ : HASHTBLSZ
bits : 24 - 25 (2 bit)

L3L4FNUM : L3L4FNUM
bits : 27 - 30 (4 bit)


MACHWF2R

HW feature 2 register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MACHWF2R MACHWF2R read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXQCNT TXQCNT RXCHCNT TXCHCNT PPSOUTNUM AUXSNAPNUM

RXQCNT : RXQCNT
bits : 0 - 3 (4 bit)

TXQCNT : TXQCNT
bits : 6 - 9 (4 bit)

RXCHCNT : RXCHCNT
bits : 12 - 15 (4 bit)

TXCHCNT : TXCHCNT
bits : 18 - 21 (4 bit)

PPSOUTNUM : PPSOUTNUM
bits : 24 - 26 (3 bit)

AUXSNAPNUM : AUXSNAPNUM
bits : 28 - 30 (3 bit)


MACHT1R

Hash Table 1 register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACHT1R MACHT1R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HT63T32

HT63T32 : HT63T32
bits : 0 - 31 (32 bit)


MACMDIOAR

MDIO address register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACMDIOAR MACMDIOAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MB C45E GOC SKAP CR NTC RDA PA BTB PSE

MB : MB
bits : 0 - 0 (1 bit)

C45E : C45E
bits : 1 - 1 (1 bit)

GOC : GOC
bits : 2 - 3 (2 bit)

SKAP : SKAP
bits : 4 - 4 (1 bit)

CR : CR
bits : 8 - 11 (4 bit)

NTC : NTC
bits : 12 - 14 (3 bit)

RDA : RDA
bits : 16 - 20 (5 bit)

PA : PA
bits : 21 - 25 (5 bit)

BTB : BTB
bits : 26 - 26 (1 bit)

PSE : PSE
bits : 27 - 27 (1 bit)


MACMDIODR

MDIO data register
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACMDIODR MACMDIODR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MD RA

MD : MD
bits : 0 - 15 (16 bit)

RA : RA
bits : 16 - 31 (16 bit)


MACA0HR

Address 0 high register
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACA0HR MACA0HR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRHI AE

ADDRHI : ADDRHI
bits : 0 - 15 (16 bit)
access : read-write

AE : AE
bits : 31 - 31 (1 bit)
access : read-only


MACA0LR

Address 0 low register
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACA0LR MACA0LR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRLO

ADDRLO : ADDRLO
bits : 0 - 31 (32 bit)


MACA1HR

Address 1 high register
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACA1HR MACA1HR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRHI MBC SA AE

ADDRHI : ADDRHI
bits : 0 - 15 (16 bit)

MBC : MBC
bits : 24 - 29 (6 bit)

SA : SA
bits : 30 - 30 (1 bit)

AE : AE
bits : 31 - 31 (1 bit)


MACA1LR

Address 1 low register
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACA1LR MACA1LR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRLO

ADDRLO : ADDRLO
bits : 0 - 31 (32 bit)


MACA2HR

Address 2 high register
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACA2HR MACA2HR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRHI MBC SA AE

ADDRHI : ADDRHI
bits : 0 - 15 (16 bit)

MBC : MBC
bits : 24 - 29 (6 bit)

SA : SA
bits : 30 - 30 (1 bit)

AE : AE
bits : 31 - 31 (1 bit)


MACA2LR

Address 2 low register
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACA2LR MACA2LR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRLO

ADDRLO : ADDRLO
bits : 0 - 31 (32 bit)


MACA3HR

Address 3 high register
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACA3HR MACA3HR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRHI MBC SA AE

ADDRHI : ADDRHI
bits : 0 - 15 (16 bit)

MBC : MBC
bits : 24 - 29 (6 bit)

SA : SA
bits : 30 - 30 (1 bit)

AE : AE
bits : 31 - 31 (1 bit)


MACA3LR

Address 3 low register
address_offset : 0x31C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACA3LR MACA3LR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRLO

ADDRLO : ADDRLO
bits : 0 - 31 (32 bit)


MACECR

Extended operating mode configuration register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACECR MACECR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPSL DCRCC SPEN USP EIPGEN EIPG

GPSL : GPSL
bits : 0 - 13 (14 bit)

DCRCC : DCRCC
bits : 16 - 16 (1 bit)

SPEN : SPEN
bits : 17 - 17 (1 bit)

USP : USP
bits : 18 - 18 (1 bit)

EIPGEN : EIPGEN
bits : 24 - 24 (1 bit)

EIPG : EIPG
bits : 25 - 29 (5 bit)


MACVTR

VLAN tag register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACVTR MACVTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VL ETV VTIM ESVL ERSVLM DOVLTC EVLS EVLRXS VTHM EDVLP ERIVLT EIVLS EIVLRXS

VL : VL
bits : 0 - 15 (16 bit)

ETV : ETV
bits : 16 - 16 (1 bit)

VTIM : VTIM
bits : 17 - 17 (1 bit)

ESVL : ESVL
bits : 18 - 18 (1 bit)

ERSVLM : ERSVLM
bits : 19 - 19 (1 bit)

DOVLTC : DOVLTC
bits : 20 - 20 (1 bit)

EVLS : EVLS
bits : 21 - 22 (2 bit)

EVLRXS : EVLRXS
bits : 24 - 24 (1 bit)

VTHM : VTHM
bits : 25 - 25 (1 bit)

EDVLP : EDVLP
bits : 26 - 26 (1 bit)

ERIVLT : ERIVLT
bits : 27 - 27 (1 bit)

EIVLS : EIVLS
bits : 28 - 29 (2 bit)

EIVLRXS : EIVLRXS
bits : 31 - 31 (1 bit)


MACVHTR

VLAN Hash table register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACVHTR MACVHTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VLHT

VLHT : VLHT
bits : 0 - 15 (16 bit)


MACVIR

VLAN inclusion register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACVIR MACVIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VLT VLC VLP CSVL VLTI

VLT : VLT
bits : 0 - 15 (16 bit)

VLC : VLC
bits : 16 - 17 (2 bit)

VLP : VLP
bits : 18 - 18 (1 bit)

CSVL : CSVL
bits : 19 - 19 (1 bit)

VLTI : VLTI
bits : 20 - 20 (1 bit)


MACIVIR

Inner VLAN inclusion register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACIVIR MACIVIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VLT VLC VLP CSVL VLTI

VLT : VLT
bits : 0 - 15 (16 bit)

VLC : VLC
bits : 16 - 17 (2 bit)

VLP : VLP
bits : 18 - 18 (1 bit)

CSVL : CSVL
bits : 19 - 19 (1 bit)

VLTI : VLTI
bits : 20 - 20 (1 bit)


MACQTxFCR

Tx Queue flow control register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACQTxFCR MACQTxFCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FCB_BPA TFE PLT DZPQ PT

FCB_BPA : FCB_BPA
bits : 0 - 0 (1 bit)

TFE : TFE
bits : 1 - 1 (1 bit)

PLT : PLT
bits : 4 - 6 (3 bit)

DZPQ : DZPQ
bits : 7 - 7 (1 bit)

PT : PT
bits : 16 - 31 (16 bit)


MMC_CONTROL

MMC control register
address_offset : 0x700 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMC_CONTROL MMC_CONTROL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNTRST CNTSTOPRO RSTONRD CNTFREEZ CNTPRST CNTPRSTLVL UCDBC

CNTRST : CNTRST
bits : 0 - 0 (1 bit)

CNTSTOPRO : CNTSTOPRO
bits : 1 - 1 (1 bit)

RSTONRD : RSTONRD
bits : 2 - 2 (1 bit)

CNTFREEZ : CNTFREEZ
bits : 3 - 3 (1 bit)

CNTPRST : CNTPRST
bits : 4 - 4 (1 bit)

CNTPRSTLVL : CNTPRSTLVL
bits : 5 - 5 (1 bit)

UCDBC : UCDBC
bits : 8 - 8 (1 bit)


MMC_RX_INTERRUPT

MMC Rx interrupt register
address_offset : 0x704 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MMC_RX_INTERRUPT MMC_RX_INTERRUPT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXCRCERPIS RXALGNERPIS RXUCGPIS RXLPIUSCIS RXLPITRCIS

RXCRCERPIS : RXCRCERPIS
bits : 5 - 5 (1 bit)

RXALGNERPIS : RXALGNERPIS
bits : 6 - 6 (1 bit)

RXUCGPIS : RXUCGPIS
bits : 17 - 17 (1 bit)

RXLPIUSCIS : RXLPIUSCIS
bits : 26 - 26 (1 bit)

RXLPITRCIS : RXLPITRCIS
bits : 27 - 27 (1 bit)


MMC_TX_INTERRUPT

MMC Tx interrupt register
address_offset : 0x708 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MMC_TX_INTERRUPT MMC_TX_INTERRUPT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXSCOLGPIS TXMCOLGPIS TXGPKTIS TXLPIUSCIS TXLPITRCIS

TXSCOLGPIS : TXSCOLGPIS
bits : 14 - 14 (1 bit)

TXMCOLGPIS : TXMCOLGPIS
bits : 15 - 15 (1 bit)

TXGPKTIS : TXGPKTIS
bits : 21 - 21 (1 bit)

TXLPIUSCIS : TXLPIUSCIS
bits : 26 - 26 (1 bit)

TXLPITRCIS : TXLPITRCIS
bits : 27 - 27 (1 bit)


MMC_RX_INTERRUPT_MASK

MMC Rx interrupt mask register
address_offset : 0x70C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMC_RX_INTERRUPT_MASK MMC_RX_INTERRUPT_MASK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXCRCERPIM RXALGNERPIM RXUCGPIM RXLPIUSCIM RXLPITRCIM

RXCRCERPIM : RXCRCERPIM
bits : 5 - 5 (1 bit)
access : read-write

RXALGNERPIM : RXALGNERPIM
bits : 6 - 6 (1 bit)
access : read-write

RXUCGPIM : RXUCGPIM
bits : 17 - 17 (1 bit)
access : read-write

RXLPIUSCIM : RXLPIUSCIM
bits : 26 - 26 (1 bit)
access : read-write

RXLPITRCIM : RXLPITRCIM
bits : 27 - 27 (1 bit)
access : read-only


MMC_TX_INTERRUPT_MASK

MMC Tx interrupt mask register
address_offset : 0x710 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMC_TX_INTERRUPT_MASK MMC_TX_INTERRUPT_MASK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXSCOLGPIM TXMCOLGPIM TXGPKTIM TXLPIUSCIM TXLPITRCIM

TXSCOLGPIM : TXSCOLGPIM
bits : 14 - 14 (1 bit)
access : read-write

TXMCOLGPIM : TXMCOLGPIM
bits : 15 - 15 (1 bit)
access : read-write

TXGPKTIM : TXGPKTIM
bits : 21 - 21 (1 bit)
access : read-write

TXLPIUSCIM : TXLPIUSCIM
bits : 26 - 26 (1 bit)
access : read-write

TXLPITRCIM : TXLPITRCIM
bits : 27 - 27 (1 bit)
access : read-only


TX_SINGLE_COLLISION_GOOD_PACKETS (TX_SINGLE_COLLISION_GOOD_PACKETS)

Tx single collision good packets register
address_offset : 0x74C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TX_SINGLE_COLLISION_GOOD_PACKETS TX_SINGLE_COLLISION_GOOD_PACKETS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXSNGLCOLG

TXSNGLCOLG : TXSNGLCOLG
bits : 0 - 31 (32 bit)


TX_MULTIPLE_COLLISION_GOOD_PACKETS (TX_MULTIPLE_COLLISION_GOOD_PACKETS)

Tx multiple collision good packets register
address_offset : 0x750 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TX_MULTIPLE_COLLISION_GOOD_PACKETS TX_MULTIPLE_COLLISION_GOOD_PACKETS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXMULTCOLG

TXMULTCOLG : TXMULTCOLG
bits : 0 - 31 (32 bit)


TX_PACKET_COUNT_GOOD

Tx packet count good register
address_offset : 0x768 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TX_PACKET_COUNT_GOOD TX_PACKET_COUNT_GOOD read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXPKTG

TXPKTG : TXPKTG
bits : 0 - 31 (32 bit)


RX_CRC_ERROR_PACKETS

Rx CRC error packets register
address_offset : 0x794 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RX_CRC_ERROR_PACKETS RX_CRC_ERROR_PACKETS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXCRCERR

RXCRCERR : RXCRCERR
bits : 0 - 31 (32 bit)


RX_ALIGNMENT_ERROR_PACKETS

Rx alignment error packets register
address_offset : 0x798 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RX_ALIGNMENT_ERROR_PACKETS RX_ALIGNMENT_ERROR_PACKETS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXALGNERR

RXALGNERR : RXALGNERR
bits : 0 - 31 (32 bit)


RX_UNICAST_PACKETS_GOOD

Rx unicast packets good register
address_offset : 0x7C4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RX_UNICAST_PACKETS_GOOD RX_UNICAST_PACKETS_GOOD read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXUCASTG

RXUCASTG : RXUCASTG
bits : 0 - 31 (32 bit)


TX_LPI_USEC_CNTR

Tx LPI microsecond timer register
address_offset : 0x7EC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TX_LPI_USEC_CNTR TX_LPI_USEC_CNTR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXLPIUSC

TXLPIUSC : TXLPIUSC
bits : 0 - 31 (32 bit)


TX_LPI_TRAN_CNTR

Tx LPI transition counter register
address_offset : 0x7F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TX_LPI_TRAN_CNTR TX_LPI_TRAN_CNTR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXLPITRC

TXLPITRC : TXLPITRC
bits : 0 - 31 (32 bit)


RX_LPI_USEC_CNTR

Rx LPI microsecond counter register
address_offset : 0x7F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RX_LPI_USEC_CNTR RX_LPI_USEC_CNTR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXLPIUSC

RXLPIUSC : RXLPIUSC
bits : 0 - 31 (32 bit)


RX_LPI_TRAN_CNTR

Rx LPI transition counter register
address_offset : 0x7F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RX_LPI_TRAN_CNTR RX_LPI_TRAN_CNTR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXLPITRC

RXLPITRC : RXLPITRC
bits : 0 - 31 (32 bit)


MACPFR

Packet filtering control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACPFR MACPFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PR HUC HMC DAIF PM DBF PCF SAIF SAF HPF VTFE IPFE DNTU RA

PR : PR
bits : 0 - 0 (1 bit)

HUC : HUC
bits : 1 - 1 (1 bit)

HMC : HMC
bits : 2 - 2 (1 bit)

DAIF : DAIF
bits : 3 - 3 (1 bit)

PM : PM
bits : 4 - 4 (1 bit)

DBF : DBF
bits : 5 - 5 (1 bit)

PCF : PCF
bits : 6 - 7 (2 bit)

SAIF : SAIF
bits : 8 - 8 (1 bit)

SAF : SAF
bits : 9 - 9 (1 bit)

HPF : HPF
bits : 10 - 10 (1 bit)

VTFE : VTFE
bits : 16 - 16 (1 bit)

IPFE : IPFE
bits : 20 - 20 (1 bit)

DNTU : DNTU
bits : 21 - 21 (1 bit)

RA : RA
bits : 31 - 31 (1 bit)


MACRxFCR

Rx flow control register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACRxFCR MACRxFCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFE UP

RFE : RFE
bits : 0 - 0 (1 bit)

UP : UP
bits : 1 - 1 (1 bit)


MACL3L4C0R

L3 and L4 control 0 register
address_offset : 0x900 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACL3L4C0R MACL3L4C0R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L3PEN0 L3SAM0 L3SAIM0 L3DAM0 L3DAIM0 L3HSBM0 L3HDBM0 L4PEN0 L4SPM0 L4SPIM0 L4DPM0 L4DPIM0

L3PEN0 : L3PEN0
bits : 0 - 0 (1 bit)

L3SAM0 : L3SAM0
bits : 2 - 2 (1 bit)

L3SAIM0 : L3SAIM0
bits : 3 - 3 (1 bit)

L3DAM0 : L3DAM0
bits : 4 - 4 (1 bit)

L3DAIM0 : L3DAIM0
bits : 5 - 5 (1 bit)

L3HSBM0 : L3HSBM0
bits : 6 - 10 (5 bit)

L3HDBM0 : L3HDBM0
bits : 11 - 15 (5 bit)

L4PEN0 : L4PEN0
bits : 16 - 16 (1 bit)

L4SPM0 : L4SPM0
bits : 18 - 18 (1 bit)

L4SPIM0 : L4SPIM0
bits : 19 - 19 (1 bit)

L4DPM0 : L4DPM0
bits : 20 - 20 (1 bit)

L4DPIM0 : L4DPIM0
bits : 21 - 21 (1 bit)


MACL4A0R

Layer4 address filter 0 register
address_offset : 0x904 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACL4A0R MACL4A0R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L4SP0 L4DP0

L4SP0 : L4SP0
bits : 0 - 15 (16 bit)

L4DP0 : L4DP0
bits : 16 - 31 (16 bit)


MACL3A00R

MACL3A00R
address_offset : 0x910 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACL3A00R MACL3A00R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L3A00

L3A00 : L3A00
bits : 0 - 31 (32 bit)


MACL3A10R

Layer3 address 1 filter 0 register
address_offset : 0x914 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACL3A10R MACL3A10R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L3A10

L3A10 : L3A10
bits : 0 - 31 (32 bit)


MACL3A20

Layer3 Address 2 filter 0 register
address_offset : 0x918 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACL3A20 MACL3A20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L3A20

L3A20 : L3A20
bits : 0 - 31 (32 bit)


MACL3A30

Layer3 Address 3 filter 0 register
address_offset : 0x91C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACL3A30 MACL3A30 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L3A30

L3A30 : L3A30
bits : 0 - 31 (32 bit)


MACL3L4C1R

L3 and L4 control 1 register
address_offset : 0x930 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACL3L4C1R MACL3L4C1R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L3PEN1 L3SAM1 L3SAIM1 L3DAM1 L3DAIM1 L3HSBM1 L3HDBM1 L4PEN1 L4SPM1 L4SPIM1 L4DPM1 L4DPIM1

L3PEN1 : L3PEN1
bits : 0 - 0 (1 bit)

L3SAM1 : L3SAM1
bits : 2 - 2 (1 bit)

L3SAIM1 : L3SAIM1
bits : 3 - 3 (1 bit)

L3DAM1 : L3DAM1
bits : 4 - 4 (1 bit)

L3DAIM1 : L3DAIM1
bits : 5 - 5 (1 bit)

L3HSBM1 : L3HSBM1
bits : 6 - 10 (5 bit)

L3HDBM1 : L3HDBM1
bits : 11 - 15 (5 bit)

L4PEN1 : L4PEN1
bits : 16 - 16 (1 bit)

L4SPM1 : L4SPM1
bits : 18 - 18 (1 bit)

L4SPIM1 : L4SPIM1
bits : 19 - 19 (1 bit)

L4DPM1 : L4DPM1
bits : 20 - 20 (1 bit)

L4DPIM1 : L4DPIM1
bits : 21 - 21 (1 bit)


MACL4A1R

Layer 4 address filter 1 register
address_offset : 0x934 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACL4A1R MACL4A1R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L4SP1 L4DP1

L4SP1 : L4SP1
bits : 0 - 15 (16 bit)

L4DP1 : L4DP1
bits : 16 - 31 (16 bit)


MACL3A01R

Layer3 address 0 filter 1 Register
address_offset : 0x940 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACL3A01R MACL3A01R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L3A01

L3A01 : L3A01
bits : 0 - 31 (32 bit)


MACL3A11R

Layer3 address 1 filter 1 register
address_offset : 0x944 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACL3A11R MACL3A11R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L3A11

L3A11 : L3A11
bits : 0 - 31 (32 bit)


MACL3A21R

Layer3 address 2 filter 1 Register
address_offset : 0x948 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACL3A21R MACL3A21R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L3A21

L3A21 : L3A21
bits : 0 - 31 (32 bit)


MACL3A31R

Layer3 address 3 filter 1 register
address_offset : 0x94C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACL3A31R MACL3A31R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L3A31

L3A31 : L3A31
bits : 0 - 31 (32 bit)


MACARPAR

ARP address register
address_offset : 0xAE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACARPAR MACARPAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARPPA

ARPPA : ARPPA
bits : 0 - 31 (32 bit)


MACISR

Interrupt status register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MACISR MACISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PHYIS PMTIS LPIIS MMCIS MMCRXIS MMCTXIS TSIS TXSTSIS RXSTSIS

PHYIS : PHYIS
bits : 3 - 3 (1 bit)

PMTIS : PMTIS
bits : 4 - 4 (1 bit)

LPIIS : LPIIS
bits : 5 - 5 (1 bit)

MMCIS : MMCIS
bits : 8 - 8 (1 bit)

MMCRXIS : MMCRXIS
bits : 9 - 9 (1 bit)

MMCTXIS : MMCTXIS
bits : 10 - 10 (1 bit)

TSIS : TSIS
bits : 12 - 12 (1 bit)

TXSTSIS : TXSTSIS
bits : 13 - 13 (1 bit)

RXSTSIS : RXSTSIS
bits : 14 - 14 (1 bit)


MACTSCR

Timestamp control Register
address_offset : 0xB00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACTSCR MACTSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSENA TSCFUPDT TSINIT TSUPDT TSADDREG TSENALL TSCTRLSSR TSVER2ENA TSIPENA TSIPV6ENA TSIPV4ENA TSEVNTENA TSMSTRENA SNAPTYPSEL TSENMACADDR CSC TXTSSTSM

TSENA : TSENA
bits : 0 - 0 (1 bit)
access : read-write

TSCFUPDT : TSCFUPDT
bits : 1 - 1 (1 bit)
access : read-write

TSINIT : TSINIT
bits : 2 - 2 (1 bit)
access : read-write

TSUPDT : TSUPDT
bits : 3 - 3 (1 bit)
access : read-write

TSADDREG : TSADDREG
bits : 5 - 5 (1 bit)
access : read-write

TSENALL : TSENALL
bits : 8 - 8 (1 bit)
access : read-write

TSCTRLSSR : TSCTRLSSR
bits : 9 - 9 (1 bit)
access : read-write

TSVER2ENA : TSVER2ENA
bits : 10 - 10 (1 bit)
access : read-write

TSIPENA : TSIPENA
bits : 11 - 11 (1 bit)
access : read-write

TSIPV6ENA : TSIPV6ENA
bits : 12 - 12 (1 bit)
access : read-write

TSIPV4ENA : TSIPV4ENA
bits : 13 - 13 (1 bit)
access : read-write

TSEVNTENA : TSEVNTENA
bits : 14 - 14 (1 bit)
access : read-write

TSMSTRENA : TSMSTRENA
bits : 15 - 15 (1 bit)
access : read-write

SNAPTYPSEL : SNAPTYPSEL
bits : 16 - 17 (2 bit)
access : read-write

TSENMACADDR : TSENMACADDR
bits : 18 - 18 (1 bit)
access : read-write

CSC : CSC
bits : 19 - 19 (1 bit)
access : read-only

TXTSSTSM : TXTSSTSM
bits : 24 - 24 (1 bit)
access : read-write


MACSSIR

Sub-second increment register
address_offset : 0xB04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACSSIR MACSSIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SNSINC SSINC

SNSINC : SNSINC
bits : 8 - 15 (8 bit)

SSINC : SSINC
bits : 16 - 23 (8 bit)


MACSTSR

System time seconds register
address_offset : 0xB08 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MACSTSR MACSTSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSS

TSS : TSS
bits : 0 - 31 (32 bit)


MACSTNR

System time nanoseconds register
address_offset : 0xB0C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MACSTNR MACSTNR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSSS

TSSS : TSSS
bits : 0 - 30 (31 bit)


MACSTSUR

System time seconds update register
address_offset : 0xB10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACSTSUR MACSTSUR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSS

TSS : TSS
bits : 0 - 31 (32 bit)


MACSTNUR

System time nanoseconds update register
address_offset : 0xB14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACSTNUR MACSTNUR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSSS ADDSUB

TSSS : TSSS
bits : 0 - 30 (31 bit)

ADDSUB : ADDSUB
bits : 31 - 31 (1 bit)


MACTSAR

Timestamp addend register
address_offset : 0xB18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACTSAR MACTSAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSAR

TSAR : TSAR
bits : 0 - 31 (32 bit)


MACTSSR

Timestamp status register
address_offset : 0xB20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MACTSSR MACTSSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSSOVF TSTARGT0 AUXTSTRIG TSTRGTERR0 TXTSSIS ATSSTN ATSSTM ATSNS

TSSOVF : TSSOVF
bits : 0 - 0 (1 bit)

TSTARGT0 : TSTARGT0
bits : 1 - 1 (1 bit)

AUXTSTRIG : AUXTSTRIG
bits : 2 - 2 (1 bit)

TSTRGTERR0 : TSTRGTERR0
bits : 3 - 3 (1 bit)

TXTSSIS : TXTSSIS
bits : 15 - 15 (1 bit)

ATSSTN : ATSSTN
bits : 16 - 19 (4 bit)

ATSSTM : ATSSTM
bits : 24 - 24 (1 bit)

ATSNS : ATSNS
bits : 25 - 29 (5 bit)


MACTxTSSNR

Tx timestamp status nanoseconds register
address_offset : 0xB30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MACTxTSSNR MACTxTSSNR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXTSSLO TXTSSMIS

TXTSSLO : TXTSSLO
bits : 0 - 30 (31 bit)

TXTSSMIS : TXTSSMIS
bits : 31 - 31 (1 bit)


MACTxTSSSR

Tx timestamp status seconds register
address_offset : 0xB34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MACTxTSSSR MACTxTSSSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXTSSHI

TXTSSHI : TXTSSHI
bits : 0 - 31 (32 bit)


MACIER

Interrupt enable register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACIER MACIER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PHYIE PMTIE LPIIE TSIE TXSTSIE RXSTSIE

PHYIE : PHYIE
bits : 3 - 3 (1 bit)

PMTIE : PMTIE
bits : 4 - 4 (1 bit)

LPIIE : LPIIE
bits : 5 - 5 (1 bit)

TSIE : TSIE
bits : 12 - 12 (1 bit)

TXSTSIE : TXSTSIE
bits : 13 - 13 (1 bit)

RXSTSIE : RXSTSIE
bits : 14 - 14 (1 bit)


MACACR

Auxiliary control register
address_offset : 0xB40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACACR MACACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ATSFC ATSEN0 ATSEN1 ATSEN2 ATSEN3

ATSFC : ATSFC
bits : 0 - 0 (1 bit)

ATSEN0 : ATSEN0
bits : 4 - 4 (1 bit)

ATSEN1 : ATSEN1
bits : 5 - 5 (1 bit)

ATSEN2 : ATSEN2
bits : 6 - 6 (1 bit)

ATSEN3 : ATSEN3
bits : 7 - 7 (1 bit)


MACATSNR

Auxiliary timestamp nanoseconds register
address_offset : 0xB48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MACATSNR MACATSNR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AUXTSLO

AUXTSLO : AUXTSLO
bits : 0 - 30 (31 bit)


MACATSSR

Auxiliary timestamp seconds register
address_offset : 0xB4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MACATSSR MACATSSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AUXTSHI

AUXTSHI : AUXTSHI
bits : 0 - 31 (32 bit)


MACTSIACR

Timestamp Ingress asymmetric correction register
address_offset : 0xB50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACTSIACR MACTSIACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OSTIAC

OSTIAC : OSTIAC
bits : 0 - 31 (32 bit)


MACTSEACR

Timestamp Egress asymmetric correction register
address_offset : 0xB54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACTSEACR MACTSEACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OSTEAC

OSTEAC : OSTEAC
bits : 0 - 31 (32 bit)


MACTSICNR

Timestamp Ingress correction nanosecond register
address_offset : 0xB58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACTSICNR MACTSICNR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSIC

TSIC : TSIC
bits : 0 - 31 (32 bit)


MACTSECNR

Timestamp Egress correction nanosecond register
address_offset : 0xB5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACTSECNR MACTSECNR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSEC

TSEC : TSEC
bits : 0 - 31 (32 bit)


MACPPSCR

PPS control register
address_offset : 0xB70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACPPSCR MACPPSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PPSCTRL PPSEN0 TRGTMODSEL0

PPSCTRL : PPSCTRL
bits : 0 - 3 (4 bit)

PPSEN0 : PPSEN0
bits : 4 - 4 (1 bit)

TRGTMODSEL0 : TRGTMODSEL0
bits : 5 - 6 (2 bit)


MACRxTxSR

Rx Tx status register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MACRxTxSR MACRxTxSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TJT NCARR LCARR EXDEF LCOL EXCOL RWT

TJT : TJT
bits : 0 - 0 (1 bit)

NCARR : NCARR
bits : 1 - 1 (1 bit)

LCARR : LCARR
bits : 2 - 2 (1 bit)

EXDEF : EXDEF
bits : 3 - 3 (1 bit)

LCOL : LCOL
bits : 4 - 4 (1 bit)

EXCOL : LCOL
bits : 5 - 5 (1 bit)

RWT : RWT
bits : 8 - 8 (1 bit)


MACPPSTTSR

PPS target time seconds register
address_offset : 0xB80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACPPSTTSR MACPPSTTSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSTRH0

TSTRH0 : TSTRH0
bits : 0 - 30 (31 bit)


MACPPSTTNR

PPS target time nanoseconds register
address_offset : 0xB84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACPPSTTNR MACPPSTTNR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TTSL0 TRGTBUSY0

TTSL0 : TTSL0
bits : 0 - 30 (31 bit)

TRGTBUSY0 : TRGTBUSY0
bits : 31 - 31 (1 bit)


MACPPSIR

PPS interval register
address_offset : 0xB88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACPPSIR MACPPSIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PPSINT0

PPSINT0 : PPSINT0
bits : 0 - 31 (32 bit)


MACPPSWR

PPS width register
address_offset : 0xB8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACPPSWR MACPPSWR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PPSWIDTH0

PPSWIDTH0 : PPSWIDTH0
bits : 0 - 31 (32 bit)


MACPOCR

PTP Offload control register
address_offset : 0xBC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACPOCR MACPOCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PTOEN ASYNCEN APDREQEN ASYNCTRIG APDREQTRIG DRRDIS DN

PTOEN : PTOEN
bits : 0 - 0 (1 bit)

ASYNCEN : ASYNCEN
bits : 1 - 1 (1 bit)

APDREQEN : APDREQEN
bits : 2 - 2 (1 bit)

ASYNCTRIG : ASYNCTRIG
bits : 4 - 4 (1 bit)

APDREQTRIG : APDREQTRIG
bits : 5 - 5 (1 bit)

DRRDIS : DRRDIS
bits : 6 - 6 (1 bit)

DN : DN
bits : 8 - 15 (8 bit)


MACSPI0R

PTP Source Port Identity 0 Register
address_offset : 0xBC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACSPI0R MACSPI0R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPI0

SPI0 : SPI0
bits : 0 - 31 (32 bit)


MACSPI1R

PTP Source port identity 1 register
address_offset : 0xBC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACSPI1R MACSPI1R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPI1

SPI1 : SPI1
bits : 0 - 31 (32 bit)


MACSPI2R

PTP Source port identity 2 register
address_offset : 0xBCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACSPI2R MACSPI2R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPI2

SPI2 : SPI2
bits : 0 - 15 (16 bit)


MACLMIR

Log message interval register
address_offset : 0xBD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACLMIR MACLMIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSI DRSYNCR LMPDRI

LSI : LSI
bits : 0 - 7 (8 bit)

DRSYNCR : DRSYNCR
bits : 8 - 10 (3 bit)

LMPDRI : LMPDRI
bits : 24 - 31 (8 bit)


MACWTR

Watchdog timeout register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACWTR MACWTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WTO PWE

WTO : WTO
bits : 0 - 3 (4 bit)

PWE : PWE
bits : 8 - 8 (1 bit)


MACPCSR

PMT control status register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACPCSR MACPCSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWRDWN MGKPKTEN RWKPKTEN MGKPRCVD RWKPRCVD GLBLUCAST RWKPFE RWKPTR RWKFILTRST

PWRDWN : PWRDWN
bits : 0 - 0 (1 bit)
access : read-write

MGKPKTEN : MGKPKTEN
bits : 1 - 1 (1 bit)
access : read-write

RWKPKTEN : RWKPKTEN
bits : 2 - 2 (1 bit)
access : read-write

MGKPRCVD : MGKPRCVD
bits : 5 - 5 (1 bit)
access : read-only

RWKPRCVD : RWKPRCVD
bits : 6 - 6 (1 bit)
access : read-only

GLBLUCAST : GLBLUCAST
bits : 9 - 9 (1 bit)
access : read-write

RWKPFE : RWKPFE
bits : 10 - 10 (1 bit)
access : read-write

RWKPTR : RWKPTR
bits : 24 - 28 (5 bit)
access : read-write

RWKFILTRST : RWKFILTRST
bits : 31 - 31 (1 bit)
access : read-write


MTLOMR

Operating mode Register
address_offset : 0xC00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MTLOMR MTLOMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTXSTS CNTPRST CNTCLR

DTXSTS : DTXSTS
bits : 1 - 1 (1 bit)

CNTPRST : CNTPRST
bits : 8 - 8 (1 bit)

CNTCLR : CNTCLR
bits : 9 - 9 (1 bit)


MTLISR

Interrupt status Register
address_offset : 0xC20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MTLISR MTLISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Q0IS

Q0IS : Queue interrupt status
bits : 0 - 0 (1 bit)


MACRWKPFR

Remove wakeup packet filter register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACRWKPFR MACRWKPFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WKUPFRMFTR

WKUPFRMFTR : WKUPFRMFTR
bits : 0 - 31 (32 bit)


MACLCSR

LPI control status register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACLCSR MACLCSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TLPIEN TLPIEX RLPIEN RLPIEX TLPIST RLPIST LPIEN PLS PLSEN LPITXA LPITE LPITCSE

TLPIEN : TLPIEN
bits : 0 - 0 (1 bit)
access : read-only

TLPIEX : TLPIEX
bits : 1 - 1 (1 bit)
access : read-only

RLPIEN : RLPIEN
bits : 2 - 2 (1 bit)
access : read-only

RLPIEX : RLPIEX
bits : 3 - 3 (1 bit)
access : read-only

TLPIST : TLPIST
bits : 8 - 8 (1 bit)
access : read-only

RLPIST : RLPIST
bits : 9 - 9 (1 bit)
access : read-only

LPIEN : LPIEN
bits : 16 - 16 (1 bit)
access : read-write

PLS : PLS
bits : 17 - 17 (1 bit)
access : read-write

PLSEN : PLSEN
bits : 18 - 18 (1 bit)
access : read-write

LPITXA : LPITXA
bits : 19 - 19 (1 bit)
access : read-write

LPITE : LPITE
bits : 20 - 20 (1 bit)
access : read-write

LPITCSE : LPITCSE
bits : 21 - 21 (1 bit)
access : read-write


MTLTxQOMR

Tx queue operating mode Register
address_offset : 0xD00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MTLTxQOMR MTLTxQOMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTQ TSF TXQEN TTC TQS

FTQ : Flush Transmit Queue
bits : 0 - 0 (1 bit)
access : read-write

TSF : Transmit Store and Forward
bits : 1 - 1 (1 bit)
access : read-write

TXQEN : Transmit Queue Enable
bits : 2 - 3 (2 bit)
access : read-only

TTC : Transmit Threshold Control
bits : 4 - 6 (3 bit)
access : read-write

TQS : Transmit Queue Size
bits : 16 - 24 (9 bit)
access : read-write


MTLTxQUR

Tx queue underflow register
address_offset : 0xD04 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MTLTxQUR MTLTxQUR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UFFRMCNT UFCNTOVF

UFFRMCNT : Underflow Packet Counter
bits : 0 - 10 (11 bit)

UFCNTOVF : UFCNTOVF
bits : 11 - 11 (1 bit)


MTLTxQDR

Tx queue debug Register
address_offset : 0xD08 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MTLTxQDR MTLTxQDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXQPAUSED TRCSTS TWCSTS TXQSTS TXSTSFSTS PTXQ STXSTSF

TXQPAUSED : TXQPAUSED
bits : 0 - 0 (1 bit)

TRCSTS : TRCSTS
bits : 1 - 2 (2 bit)

TWCSTS : TWCSTS
bits : 3 - 3 (1 bit)

TXQSTS : TXQSTS
bits : 4 - 4 (1 bit)

TXSTSFSTS : TXSTSFSTS
bits : 5 - 5 (1 bit)

PTXQ : PTXQ
bits : 16 - 18 (3 bit)

STXSTSF : STXSTSF
bits : 20 - 22 (3 bit)


MTLQICSR

Queue interrupt control status Register
address_offset : 0xD2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MTLQICSR MTLQICSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXUNFIS TXUIE RXOVFIS RXOIE

TXUNFIS : TXUNFIS
bits : 0 - 0 (1 bit)

TXUIE : TXUIE
bits : 8 - 8 (1 bit)

RXOVFIS : RXOVFIS
bits : 16 - 16 (1 bit)

RXOIE : RXOIE
bits : 24 - 24 (1 bit)


MTLRxQOMR

Rx queue operating mode register
address_offset : 0xD30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MTLRxQOMR MTLRxQOMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RTC FUP FEP RSF DIS_TCP_EF EHFC RFA RFD RQS

RTC : RTC
bits : 0 - 1 (2 bit)
access : read-write

FUP : FUP
bits : 3 - 3 (1 bit)
access : read-write

FEP : FEP
bits : 4 - 4 (1 bit)
access : read-write

RSF : RSF
bits : 5 - 5 (1 bit)
access : read-write

DIS_TCP_EF : DIS_TCP_EF
bits : 6 - 6 (1 bit)
access : read-write

EHFC : EHFC
bits : 7 - 7 (1 bit)
access : read-write

RFA : RFA
bits : 8 - 10 (3 bit)
access : read-write

RFD : RFD
bits : 14 - 16 (3 bit)
access : read-write

RQS : RQS
bits : 20 - 22 (3 bit)
access : read-only


MTLRxQMPOCR

Rx queue missed packet and overflow counter register
address_offset : 0xD34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MTLRxQMPOCR MTLRxQMPOCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVFPKTCNT OVFCNTOVF MISPKTCNT MISCNTOVF

OVFPKTCNT : OVFPKTCNT
bits : 0 - 10 (11 bit)

OVFCNTOVF : OVFCNTOVF
bits : 11 - 11 (1 bit)

MISPKTCNT : MISPKTCNT
bits : 16 - 26 (11 bit)

MISCNTOVF : MISCNTOVF
bits : 27 - 27 (1 bit)


MTLRxQDR

Rx queue debug register
address_offset : 0xD38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MTLRxQDR MTLRxQDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RWCSTS RRCSTS RXQSTS PRXQ

RWCSTS : RWCSTS
bits : 0 - 0 (1 bit)

RRCSTS : RRCSTS
bits : 1 - 2 (2 bit)

RXQSTS : RXQSTS
bits : 4 - 5 (2 bit)

PRXQ : PRXQ
bits : 16 - 29 (14 bit)


MACLTCR

LPI timers control register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACLTCR MACLTCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TWT LST

TWT : TWT
bits : 0 - 15 (16 bit)

LST : LST
bits : 16 - 25 (10 bit)


MACLETR

LPI entry timer register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACLETR MACLETR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPIET

LPIET : LPIET
bits : 0 - 16 (17 bit)


MAC1USTCR

1-microsecond-tick counter register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAC1USTCR MAC1USTCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIC_1US_CNTR

TIC_1US_CNTR : TIC_1US_CNTR
bits : 0 - 11 (12 bit)



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