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USB_OTG_HS

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

OTG_HS_GOTGCTL

OTG_HS_GRSTCTL

OTG_HS_HPTXFSIZ

OTG_HS_DIEPTXF1

OTG_HS_DIEPTXF2

OTG_HS_DIEPTXF3

OTG_HS_DIEPTXF4

OTG_HS_DIEPTXF5

OTG_HS_DIEPTXF6

OTG_HS_DIEPTXF7

OTG_HS_DIEPTXF8

OTG_HS_GINTSTS

OTG_HS_GINTMSK

OTG_HS_GRXSTSR_Host

OTG_HS_GRXSTSR_Device

OTG_HS_GRXSTSP_Host

OTG_HS_GRXSTSP_Device

OTG_HS_GRXFSIZ

OTG_HS_HNPTXFSIZ_Host

OTG_HS_DIEPTXF0_Device

OTG_HS_HNPTXSTS

OTG_HS_GI2CCTL

OTG_HS_GCCFG

OTG_HS_CID

OTG_HS_GOTGINT

OTG_HS_GLPMCFG

OTG_HS_GAHBCFG

OTG_HS_GUSBCFG


OTG_HS_GOTGCTL

OTG_HS control and status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_GOTGCTL OTG_HS_GOTGCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRQSCS SRQ HNGSCS HNPRQ HSHNPEN DHNPEN EHEN CIDSTS DBCT ASVLD BSVLD

SRQSCS : Session request success
bits : 0 - 0 (1 bit)
access : read-only

SRQ : Session request
bits : 1 - 1 (1 bit)
access : read-write

HNGSCS : Host negotiation success
bits : 8 - 8 (1 bit)
access : read-only

HNPRQ : HNP request
bits : 9 - 9 (1 bit)
access : read-write

HSHNPEN : Host set HNP enable
bits : 10 - 10 (1 bit)
access : read-write

DHNPEN : Device HNP enabled
bits : 11 - 11 (1 bit)
access : read-write

EHEN : Embedded host enable
bits : 12 - 12 (1 bit)
access : read-write

CIDSTS : Connector ID status
bits : 16 - 16 (1 bit)
access : read-only

DBCT : Long/short debounce time
bits : 17 - 17 (1 bit)
access : read-only

ASVLD : A-session valid
bits : 18 - 18 (1 bit)
access : read-only

BSVLD : B-session valid
bits : 19 - 19 (1 bit)
access : read-only


OTG_HS_GRSTCTL

OTG_HS reset register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_GRSTCTL OTG_HS_GRSTCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSRST HSRST FCRST RXFFLSH TXFFLSH TXFNUM DMAREQ AHBIDL

CSRST : Core soft reset
bits : 0 - 0 (1 bit)
access : read-write

HSRST : HCLK soft reset
bits : 1 - 1 (1 bit)
access : read-write

FCRST : Host frame counter reset
bits : 2 - 2 (1 bit)
access : read-write

RXFFLSH : RxFIFO flush
bits : 4 - 4 (1 bit)
access : read-write

TXFFLSH : TxFIFO flush
bits : 5 - 5 (1 bit)
access : read-write

TXFNUM : TxFIFO number
bits : 6 - 10 (5 bit)
access : read-write

DMAREQ : DMA request signal enabled for USB OTG HS
bits : 30 - 30 (1 bit)
access : read-only

AHBIDL : AHB master idle
bits : 31 - 31 (1 bit)
access : read-only


OTG_HS_HPTXFSIZ

OTG_HS Host periodic transmit FIFO size register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HPTXFSIZ OTG_HS_HPTXFSIZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PTXSA PTXFD

PTXSA : Host periodic TxFIFO start address
bits : 0 - 15 (16 bit)

PTXFD : Host periodic TxFIFO depth
bits : 16 - 31 (16 bit)


OTG_HS_DIEPTXF1

OTG_HS device IN endpoint transmit FIFO size register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DIEPTXF1 OTG_HS_DIEPTXF1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INEPTXSA INEPTXFD

INEPTXSA : IN endpoint FIFOx transmit RAM start address
bits : 0 - 15 (16 bit)

INEPTXFD : IN endpoint TxFIFO depth
bits : 16 - 31 (16 bit)


OTG_HS_DIEPTXF2

OTG_HS device IN endpoint transmit FIFO size register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DIEPTXF2 OTG_HS_DIEPTXF2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INEPTXSA INEPTXFD

INEPTXSA : IN endpoint FIFOx transmit RAM start address
bits : 0 - 15 (16 bit)

INEPTXFD : IN endpoint TxFIFO depth
bits : 16 - 31 (16 bit)


OTG_HS_DIEPTXF3

OTG_HS device IN endpoint transmit FIFO size register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DIEPTXF3 OTG_HS_DIEPTXF3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INEPTXSA INEPTXFD

INEPTXSA : IN endpoint FIFOx transmit RAM start address
bits : 0 - 15 (16 bit)

INEPTXFD : IN endpoint TxFIFO depth
bits : 16 - 31 (16 bit)


OTG_HS_DIEPTXF4

OTG_HS device IN endpoint transmit FIFO size register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DIEPTXF4 OTG_HS_DIEPTXF4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INEPTXSA INEPTXFD

INEPTXSA : IN endpoint FIFOx transmit RAM start address
bits : 0 - 15 (16 bit)

INEPTXFD : IN endpoint TxFIFO depth
bits : 16 - 31 (16 bit)


OTG_HS_DIEPTXF5

OTG_HS device IN endpoint transmit FIFO size register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DIEPTXF5 OTG_HS_DIEPTXF5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INEPTXSA INEPTXFD

INEPTXSA : IN endpoint FIFOx transmit RAM start address
bits : 0 - 15 (16 bit)

INEPTXFD : IN endpoint TxFIFO depth
bits : 16 - 31 (16 bit)


OTG_HS_DIEPTXF6

OTG_HS device IN endpoint transmit FIFO size register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DIEPTXF6 OTG_HS_DIEPTXF6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INEPTXSA INEPTXFD

INEPTXSA : IN endpoint FIFOx transmit RAM start address
bits : 0 - 15 (16 bit)

INEPTXFD : IN endpoint TxFIFO depth
bits : 16 - 31 (16 bit)


OTG_HS_DIEPTXF7

OTG_HS device IN endpoint transmit FIFO size register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DIEPTXF7 OTG_HS_DIEPTXF7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INEPTXSA INEPTXFD

INEPTXSA : IN endpoint FIFOx transmit RAM start address
bits : 0 - 15 (16 bit)

INEPTXFD : IN endpoint TxFIFO depth
bits : 16 - 31 (16 bit)


OTG_HS_DIEPTXF8

OTG_HS device IN endpoint transmit FIFO size register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DIEPTXF8 OTG_HS_DIEPTXF8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OTG_HS_GINTSTS

OTG_HS core interrupt register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_GINTSTS OTG_HS_GINTSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMOD MMIS OTGINT SOF RXFLVL NPTXFE GINAKEFF BOUTNAKEFF ESUSP USBSUSP USBRST ENUMDNE ISOODRP EOPF IEPINT OEPINT IISOIXFR PXFR_INCOMPISOOUT DATAFSUSP HPRTINT HCINT PTXFE CIDSCHG DISCINT SRQINT WKUINT

CMOD : Current mode of operation
bits : 0 - 0 (1 bit)
access : read-only

MMIS : Mode mismatch interrupt
bits : 1 - 1 (1 bit)
access : read-write

OTGINT : OTG interrupt
bits : 2 - 2 (1 bit)
access : read-only

SOF : Start of frame
bits : 3 - 3 (1 bit)
access : read-write

RXFLVL : RxFIFO nonempty
bits : 4 - 4 (1 bit)
access : read-only

NPTXFE : Nonperiodic TxFIFO empty
bits : 5 - 5 (1 bit)
access : read-only

GINAKEFF : Global IN nonperiodic NAK effective
bits : 6 - 6 (1 bit)
access : read-only

BOUTNAKEFF : Global OUT NAK effective
bits : 7 - 7 (1 bit)
access : read-only

ESUSP : Early suspend
bits : 10 - 10 (1 bit)
access : read-write

USBSUSP : USB suspend
bits : 11 - 11 (1 bit)
access : read-write

USBRST : USB reset
bits : 12 - 12 (1 bit)
access : read-write

ENUMDNE : Enumeration done
bits : 13 - 13 (1 bit)
access : read-write

ISOODRP : Isochronous OUT packet dropped interrupt
bits : 14 - 14 (1 bit)
access : read-write

EOPF : End of periodic frame interrupt
bits : 15 - 15 (1 bit)
access : read-write

IEPINT : IN endpoint interrupt
bits : 18 - 18 (1 bit)
access : read-only

OEPINT : OUT endpoint interrupt
bits : 19 - 19 (1 bit)
access : read-only

IISOIXFR : Incomplete isochronous IN transfer
bits : 20 - 20 (1 bit)
access : read-write

PXFR_INCOMPISOOUT : Incomplete periodic transfer
bits : 21 - 21 (1 bit)
access : read-write

DATAFSUSP : Data fetch suspended
bits : 22 - 22 (1 bit)
access : read-write

HPRTINT : Host port interrupt
bits : 24 - 24 (1 bit)
access : read-only

HCINT : Host channels interrupt
bits : 25 - 25 (1 bit)
access : read-only

PTXFE : Periodic TxFIFO empty
bits : 26 - 26 (1 bit)
access : read-only

CIDSCHG : Connector ID status change
bits : 28 - 28 (1 bit)
access : read-write

DISCINT : Disconnect detected interrupt
bits : 29 - 29 (1 bit)
access : read-write

SRQINT : Session request/new session detected interrupt
bits : 30 - 30 (1 bit)
access : read-write

WKUINT : Resume/remote wakeup detected interrupt
bits : 31 - 31 (1 bit)
access : read-write


OTG_HS_GINTMSK

OTG_HS interrupt mask register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_GINTMSK OTG_HS_GINTMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MMISM OTGINT SOFM RXFLVLM NPTXFEM GINAKEFFM GONAKEFFM ESUSPM USBSUSPM USBRST ENUMDNEM ISOODRPM EOPFM IEPINT OEPINT IISOIXFRM PXFRM_IISOOXFRM FSUSPM RSTDE PRTIM HCIM PTXFEM LPMINTM CIDSCHGM DISCINT SRQIM WUIM

MMISM : Mode mismatch interrupt mask
bits : 1 - 1 (1 bit)
access : read-write

OTGINT : OTG interrupt mask
bits : 2 - 2 (1 bit)
access : read-write

SOFM : Start of frame mask
bits : 3 - 3 (1 bit)
access : read-write

RXFLVLM : Receive FIFO nonempty mask
bits : 4 - 4 (1 bit)
access : read-write

NPTXFEM : Nonperiodic TxFIFO empty mask
bits : 5 - 5 (1 bit)
access : read-write

GINAKEFFM : Global nonperiodic IN NAK effective mask
bits : 6 - 6 (1 bit)
access : read-write

GONAKEFFM : Global OUT NAK effective mask
bits : 7 - 7 (1 bit)
access : read-write

ESUSPM : Early suspend mask
bits : 10 - 10 (1 bit)
access : read-write

USBSUSPM : USB suspend mask
bits : 11 - 11 (1 bit)
access : read-write

USBRST : USB reset mask
bits : 12 - 12 (1 bit)
access : read-write

ENUMDNEM : Enumeration done mask
bits : 13 - 13 (1 bit)
access : read-write

ISOODRPM : Isochronous OUT packet dropped interrupt mask
bits : 14 - 14 (1 bit)
access : read-write

EOPFM : End of periodic frame interrupt mask
bits : 15 - 15 (1 bit)
access : read-write

IEPINT : IN endpoints interrupt mask
bits : 18 - 18 (1 bit)
access : read-write

OEPINT : OUT endpoints interrupt mask
bits : 19 - 19 (1 bit)
access : read-write

IISOIXFRM : Incomplete isochronous IN transfer mask
bits : 20 - 20 (1 bit)
access : read-write

PXFRM_IISOOXFRM : Incomplete periodic transfer mask
bits : 21 - 21 (1 bit)
access : read-write

FSUSPM : Data fetch suspended mask
bits : 22 - 22 (1 bit)
access : read-write

RSTDE : Reset detected interrupt mask
bits : 23 - 23 (1 bit)
access : read-write

PRTIM : Host port interrupt mask
bits : 24 - 24 (1 bit)
access : read-only

HCIM : Host channels interrupt mask
bits : 25 - 25 (1 bit)
access : read-write

PTXFEM : Periodic TxFIFO empty mask
bits : 26 - 26 (1 bit)
access : read-write

LPMINTM : LPM interrupt mask
bits : 27 - 27 (1 bit)
access : read-write

CIDSCHGM : Connector ID status change mask
bits : 28 - 28 (1 bit)
access : read-write

DISCINT : Disconnect detected interrupt mask
bits : 29 - 29 (1 bit)
access : read-write

SRQIM : Session request/new session detected interrupt mask
bits : 30 - 30 (1 bit)
access : read-write

WUIM : Resume/remote wakeup detected interrupt mask
bits : 31 - 31 (1 bit)
access : read-write


OTG_HS_GRXSTSR_Host

OTG_HS Receive status debug read register (host mode)
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_GRXSTSR_Host OTG_HS_GRXSTSR_Host read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNUM BCNT DPID PKTSTS

CHNUM : Channel number
bits : 0 - 3 (4 bit)

BCNT : Byte count
bits : 4 - 14 (11 bit)

DPID : Data PID
bits : 15 - 16 (2 bit)

PKTSTS : Packet status
bits : 17 - 20 (4 bit)


OTG_HS_GRXSTSR_Device

OTG_HS Receive status debug read register (peripheral mode mode)
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : OTG_HS_GRXSTSR_Host
reset_Mask : 0x0

OTG_HS_GRXSTSR_Device OTG_HS_GRXSTSR_Device read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPNUM BCNT DPID PKTSTS FRMNUM

EPNUM : Endpoint number
bits : 0 - 3 (4 bit)

BCNT : Byte count
bits : 4 - 14 (11 bit)

DPID : Data PID
bits : 15 - 16 (2 bit)

PKTSTS : Packet status
bits : 17 - 20 (4 bit)

FRMNUM : Frame number
bits : 21 - 24 (4 bit)


OTG_HS_GRXSTSP_Host

OTG_HS status read and pop register (host mode)
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_GRXSTSP_Host OTG_HS_GRXSTSP_Host read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNUM BCNT DPID PKTSTS

CHNUM : Channel number
bits : 0 - 3 (4 bit)

BCNT : Byte count
bits : 4 - 14 (11 bit)

DPID : Data PID
bits : 15 - 16 (2 bit)

PKTSTS : Packet status
bits : 17 - 20 (4 bit)


OTG_HS_GRXSTSP_Device

OTG_HS status read and pop register (peripheral mode)
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : OTG_HS_GRXSTSP_Host
reset_Mask : 0x0

OTG_HS_GRXSTSP_Device OTG_HS_GRXSTSP_Device read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPNUM BCNT DPID PKTSTS FRMNUM

EPNUM : Endpoint number
bits : 0 - 3 (4 bit)

BCNT : Byte count
bits : 4 - 14 (11 bit)

DPID : Data PID
bits : 15 - 16 (2 bit)

PKTSTS : Packet status
bits : 17 - 20 (4 bit)

FRMNUM : Frame number
bits : 21 - 24 (4 bit)


OTG_HS_GRXFSIZ

OTG_HS Receive FIFO size register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_GRXFSIZ OTG_HS_GRXFSIZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXFD

RXFD : RxFIFO depth
bits : 0 - 15 (16 bit)


OTG_HS_HNPTXFSIZ_Host

OTG_HS nonperiodic transmit FIFO size register (host mode)
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HNPTXFSIZ_Host OTG_HS_HNPTXFSIZ_Host read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NPTXFSA NPTXFD

NPTXFSA : Nonperiodic transmit RAM start address
bits : 0 - 15 (16 bit)

NPTXFD : Nonperiodic TxFIFO depth
bits : 16 - 31 (16 bit)


OTG_HS_DIEPTXF0_Device

Endpoint 0 transmit FIFO size (peripheral mode)
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : OTG_HS_HNPTXFSIZ_Host
reset_Mask : 0x0

OTG_HS_DIEPTXF0_Device OTG_HS_DIEPTXF0_Device read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TX0FSA TX0FD

TX0FSA : Endpoint 0 transmit RAM start address
bits : 0 - 15 (16 bit)

TX0FD : Endpoint 0 TxFIFO depth
bits : 16 - 31 (16 bit)


OTG_HS_HNPTXSTS

OTG_HS nonperiodic transmit FIFO/queue status register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HNPTXSTS OTG_HS_HNPTXSTS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NPTXFSAV NPTQXSAV NPTXQTOP

NPTXFSAV : Nonperiodic TxFIFO space available
bits : 0 - 15 (16 bit)

NPTQXSAV : Nonperiodic transmit request queue space available
bits : 16 - 23 (8 bit)

NPTXQTOP : Top of the nonperiodic transmit request queue
bits : 24 - 30 (7 bit)


OTG_HS_GI2CCTL

OTG I2C access register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_GI2CCTL OTG_HS_GI2CCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RWDATA REGADDR ADDR I2CEN ACK I2CDEVADR I2CDATSE0 RW BSYDNE

RWDATA : I2C Read/Write Data
bits : 0 - 7 (8 bit)

REGADDR : I2C Register Address
bits : 8 - 15 (8 bit)

ADDR : I2C Address
bits : 16 - 22 (7 bit)

I2CEN : I2C Enable
bits : 23 - 23 (1 bit)

ACK : I2C ACK
bits : 24 - 24 (1 bit)

I2CDEVADR : I2C Device Address
bits : 26 - 27 (2 bit)

I2CDATSE0 : I2C DatSe0 USB mode
bits : 28 - 28 (1 bit)

RW : Read/Write Indicator
bits : 30 - 30 (1 bit)

BSYDNE : I2C Busy/Done
bits : 31 - 31 (1 bit)


OTG_HS_GCCFG

OTG_HS general core configuration register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_GCCFG OTG_HS_GCCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCDET PDET SDET PS2DET PWRDWN BCDEN DCDEN PDEN SDEN VBDEN

DCDET : Data contact detection (DCD) status
bits : 0 - 0 (1 bit)

PDET : Primary detection (PD) status
bits : 1 - 1 (1 bit)

SDET : Secondary detection (SD) status
bits : 2 - 2 (1 bit)

PS2DET : DM pull-up detection status
bits : 3 - 3 (1 bit)

PWRDWN : Power down
bits : 16 - 16 (1 bit)

BCDEN : Battery charging detector (BCD) enable
bits : 17 - 17 (1 bit)

DCDEN : Data contact detection (DCD) mode enable
bits : 18 - 18 (1 bit)

PDEN : Primary detection (PD) mode enable
bits : 19 - 19 (1 bit)

SDEN : Secondary detection (SD) mode enable
bits : 20 - 20 (1 bit)

VBDEN : USB VBUS detection enable
bits : 21 - 21 (1 bit)


OTG_HS_CID

OTG_HS core ID register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_CID OTG_HS_CID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRODUCT_ID

PRODUCT_ID : Product ID field
bits : 0 - 31 (32 bit)


OTG_HS_GOTGINT

OTG_HS interrupt register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_GOTGINT OTG_HS_GOTGINT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEDET SRSSCHG HNSSCHG HNGDET ADTOCHG DBCDNE IDCHNG

SEDET : Session end detected
bits : 2 - 2 (1 bit)

SRSSCHG : Session request success status change
bits : 8 - 8 (1 bit)

HNSSCHG : Host negotiation success status change
bits : 9 - 9 (1 bit)

HNGDET : Host negotiation detected
bits : 17 - 17 (1 bit)

ADTOCHG : A-device timeout change
bits : 18 - 18 (1 bit)

DBCDNE : Debounce done
bits : 19 - 19 (1 bit)

IDCHNG : ID input pin changed
bits : 20 - 20 (1 bit)


OTG_HS_GLPMCFG

OTG core LPM configuration register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_GLPMCFG OTG_HS_GLPMCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPMEN LPMACK BESL REMWAKE L1SSEN BESLTHRS L1DSEN LPMRST SLPSTS L1RSMOK LPMCHIDX LPMRCNT SNDLPM LPMRCNTSTS ENBESL

LPMEN : LPM support enable
bits : 0 - 0 (1 bit)
access : read-write

LPMACK : LPM token acknowledge enable
bits : 1 - 1 (1 bit)
access : read-write

BESL : Best effort service latency
bits : 2 - 5 (4 bit)
access : read-only

REMWAKE : bRemoteWake value
bits : 6 - 6 (1 bit)
access : read-only

L1SSEN : L1 Shallow Sleep enable
bits : 7 - 7 (1 bit)
access : read-write

BESLTHRS : BESL threshold
bits : 8 - 11 (4 bit)
access : read-write

L1DSEN : L1 deep sleep enable
bits : 12 - 12 (1 bit)
access : read-write

LPMRST : LPM response
bits : 13 - 14 (2 bit)
access : read-only

SLPSTS : Port sleep status
bits : 15 - 15 (1 bit)
access : read-only

L1RSMOK : Sleep State Resume OK
bits : 16 - 16 (1 bit)
access : read-only

LPMCHIDX : LPM Channel Index
bits : 17 - 20 (4 bit)
access : read-write

LPMRCNT : LPM retry count
bits : 21 - 23 (3 bit)
access : read-write

SNDLPM : Send LPM transaction
bits : 24 - 24 (1 bit)
access : read-write

LPMRCNTSTS : LPM retry count status
bits : 25 - 27 (3 bit)
access : read-only

ENBESL : Enable best effort service latency
bits : 28 - 28 (1 bit)
access : read-write


OTG_HS_GAHBCFG

OTG_HS AHB configuration register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_GAHBCFG OTG_HS_GAHBCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GINT HBSTLEN DMAEN TXFELVL PTXFELVL

GINT : Global interrupt mask
bits : 0 - 0 (1 bit)

HBSTLEN : Burst length/type
bits : 1 - 4 (4 bit)

DMAEN : DMA enable
bits : 5 - 5 (1 bit)

TXFELVL : TxFIFO empty level
bits : 7 - 7 (1 bit)

PTXFELVL : Periodic TxFIFO empty level
bits : 8 - 8 (1 bit)


OTG_HS_GUSBCFG

OTG_HS USB configuration register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_GUSBCFG OTG_HS_GUSBCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOCAL PHYSEL SRPCAP HNPCAP TRDT PHYLPCS ULPIFSLS ULPIAR ULPICSM ULPIEVBUSD ULPIEVBUSI TSDPS PCCI PTCI ULPIIPD FHMOD FDMOD

TOCAL : FS timeout calibration
bits : 0 - 2 (3 bit)
access : read-write

PHYSEL : USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select
bits : 6 - 6 (1 bit)
access : write-only

SRPCAP : SRP-capable
bits : 8 - 8 (1 bit)
access : read-write

HNPCAP : HNP-capable
bits : 9 - 9 (1 bit)
access : read-write

TRDT : USB turnaround time
bits : 10 - 13 (4 bit)
access : read-write

PHYLPCS : PHY Low-power clock select
bits : 15 - 15 (1 bit)
access : read-write

ULPIFSLS : ULPI FS/LS select
bits : 17 - 17 (1 bit)
access : read-write

ULPIAR : ULPI Auto-resume
bits : 18 - 18 (1 bit)
access : read-write

ULPICSM : ULPI Clock SuspendM
bits : 19 - 19 (1 bit)
access : read-write

ULPIEVBUSD : ULPI External VBUS Drive
bits : 20 - 20 (1 bit)
access : read-write

ULPIEVBUSI : ULPI external VBUS indicator
bits : 21 - 21 (1 bit)
access : read-write

TSDPS : TermSel DLine pulsing selection
bits : 22 - 22 (1 bit)
access : read-write

PCCI : Indicator complement
bits : 23 - 23 (1 bit)
access : read-write

PTCI : Indicator pass through
bits : 24 - 24 (1 bit)
access : read-write

ULPIIPD : ULPI interface protect disable
bits : 25 - 25 (1 bit)
access : read-write

FHMOD : Forced host mode
bits : 29 - 29 (1 bit)
access : read-write

FDMOD : Forced peripheral mode
bits : 30 - 30 (1 bit)
access : read-write



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