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SYSCFG

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CFGR1

EXTICR3

EXTICR4

COMP1_CTRL

COMP1_CSR

COMP2_CTRL

COMP2_CSR

CFGR3

CFGR2

EXTICR1

EXTICR2


CFGR1

SYSCFG configuration register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR1 CFGR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MEM_MODE BOOT_MODE

MEM_MODE : Memory mapping selection bits
bits : 0 - 1 (2 bit)
access : read-write

BOOT_MODE : Boot mode selected by the boot pins status bits
bits : 8 - 9 (2 bit)
access : read-only


EXTICR3

external interrupt configuration register 3
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTICR3 EXTICR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI8 EXTI9 EXTI10 EXTI11

EXTI8 : EXTI x configuration (x = 8 to 11)
bits : 0 - 3 (4 bit)

EXTI9 : EXTI x configuration (x = 8 to 11)
bits : 4 - 7 (4 bit)

EXTI10 : EXTI10
bits : 8 - 11 (4 bit)

EXTI11 : EXTI x configuration (x = 8 to 11)
bits : 12 - 15 (4 bit)


EXTICR4

external interrupt configuration register 4
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTICR4 EXTICR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI12 EXTI13 EXTI14 EXTI15

EXTI12 : EXTI12
bits : 0 - 3 (4 bit)

EXTI13 : EXTI13
bits : 4 - 7 (4 bit)

EXTI14 : EXTI14
bits : 8 - 11 (4 bit)

EXTI15 : EXTI x configuration (x = 12 to 15)
bits : 12 - 15 (4 bit)


COMP1_CTRL

Comparator 1 control and status register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMP1_CTRL COMP1_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMP1EN COMP1INNSEL COMP1WM COMP1LPTIMIN1 COMP1POLARITY COMP1VALUE COMP1LOCK

COMP1EN : Comparator 1 enable bit
bits : 0 - 0 (1 bit)

COMP1INNSEL : Comparator 1 Input Minus connection configuration bit
bits : 4 - 5 (2 bit)

COMP1WM : Comparator 1 window mode selection bit
bits : 8 - 8 (1 bit)

COMP1LPTIMIN1 : Comparator 1 LPTIM input propagation bit
bits : 12 - 12 (1 bit)

COMP1POLARITY : Comparator 1 polarity selection bit
bits : 15 - 15 (1 bit)

COMP1VALUE : Comparator 1 output status bit
bits : 30 - 30 (1 bit)

COMP1LOCK : COMP1_CSR register lock bit
bits : 31 - 31 (1 bit)


COMP1_CSR

Comparator 1 control and status register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMP1_CSR COMP1_CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMP1EN COMP1INNSEL COMP1WM COMP1LPTIMIN1 COMP1POLARITY COMP1VALUE COMP1LOCK

COMP1EN : Comparator 1 enable bit
bits : 0 - 0 (1 bit)

COMP1INNSEL : Comparator 1 Input Minus connection configuration bit
bits : 4 - 5 (2 bit)

COMP1WM : Comparator 1 window mode selection bit
bits : 8 - 8 (1 bit)

COMP1LPTIMIN1 : Comparator 1 LPTIM input propagation bit
bits : 12 - 12 (1 bit)

COMP1POLARITY : Comparator 1 polarity selection bit
bits : 15 - 15 (1 bit)

COMP1VALUE : Comparator 1 output status bit
bits : 30 - 30 (1 bit)

COMP1LOCK : COMP1_CSR register lock bit
bits : 31 - 31 (1 bit)


COMP2_CTRL

Comparator 2 control and status register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMP2_CTRL COMP2_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMP2EN COMP2SPEED COMP2INNSEL COMP2INPSEL COMP2LPTIMIN2 COMP2LPTIMIN1 COMP2POLARITY COMP2VALUE COMP2LOCK

COMP2EN : Comparator 2 enable bit
bits : 0 - 0 (1 bit)

COMP2SPEED : Comparator 2 power mode selection bit
bits : 3 - 3 (1 bit)

COMP2INNSEL : Comparator 2 Input Minus connection configuration bit
bits : 4 - 6 (3 bit)

COMP2INPSEL : Comparator 2 Input Plus connection configuration bit
bits : 8 - 10 (3 bit)

COMP2LPTIMIN2 : Comparator 2 LPTIM input 2 propagation bit
bits : 12 - 12 (1 bit)

COMP2LPTIMIN1 : Comparator 2 LPTIM input 1 propagation bit
bits : 13 - 13 (1 bit)

COMP2POLARITY : Comparator 2 polarity selection bit
bits : 15 - 15 (1 bit)

COMP2VALUE : Comparator 2 output status bit
bits : 30 - 30 (1 bit)

COMP2LOCK : COMP2_CSR register lock bit
bits : 31 - 31 (1 bit)


COMP2_CSR

Comparator 2 control and status register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMP2_CSR COMP2_CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMP2EN COMP2SPEED COMP2INNSEL COMP2INPSEL COMP2LPTIMIN2 COMP2LPTIMIN1 COMP2POLARITY COMP2VALUE COMP2LOCK

COMP2EN : Comparator 2 enable bit
bits : 0 - 0 (1 bit)

COMP2SPEED : Comparator 2 power mode selection bit
bits : 3 - 3 (1 bit)

COMP2INNSEL : Comparator 2 Input Minus connection configuration bit
bits : 4 - 6 (3 bit)

COMP2INPSEL : Comparator 2 Input Plus connection configuration bit
bits : 8 - 10 (3 bit)

COMP2LPTIMIN2 : Comparator 2 LPTIM input 2 propagation bit
bits : 12 - 12 (1 bit)

COMP2LPTIMIN1 : Comparator 2 LPTIM input 1 propagation bit
bits : 13 - 13 (1 bit)

COMP2POLARITY : Comparator 2 polarity selection bit
bits : 15 - 15 (1 bit)

COMP2VALUE : Comparator 2 output status bit
bits : 30 - 30 (1 bit)

COMP2LOCK : COMP2_CSR register lock bit
bits : 31 - 31 (1 bit)


CFGR3

SYSCFG configuration register 3
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR3 CFGR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN_BGAP SEL_VREF_OUT ENBUF_BGAP_ADC ENBUF_SENSOR_ADC ENBUF_VREFINT_COMP ENREF_RC48MHz REF_RC48MHz_RDYF SENSOR_ADC_RDYF VREFINT_ADC_RDYF VREFINT_COMP_RDYF VREFINT_RDYF REF_LOCK

EN_BGAP : Vref Enable bit
bits : 0 - 0 (1 bit)
access : read-write

SEL_VREF_OUT : BGAP_ADC connection bit
bits : 4 - 5 (2 bit)
access : read-write

ENBUF_BGAP_ADC : VREFINT reference for ADC enable bit
bits : 8 - 8 (1 bit)
access : read-write

ENBUF_SENSOR_ADC : Sensor reference for ADC enable bit
bits : 9 - 9 (1 bit)
access : read-write

ENBUF_VREFINT_COMP : VREFINT reference for comparator 2 enable bit
bits : 12 - 12 (1 bit)
access : read-write

ENREF_RC48MHz : VREFINT reference for 48 MHz RC oscillator enable bit
bits : 13 - 13 (1 bit)
access : read-write

REF_RC48MHz_RDYF : VREFINT for 48 MHz RC oscillator ready flag
bits : 26 - 26 (1 bit)
access : read-only

SENSOR_ADC_RDYF : Sensor for ADC ready flag
bits : 27 - 27 (1 bit)
access : read-only

VREFINT_ADC_RDYF : VREFINT for ADC ready flag
bits : 28 - 28 (1 bit)
access : read-only

VREFINT_COMP_RDYF : VREFINT for comparator ready flag
bits : 29 - 29 (1 bit)
access : read-only

VREFINT_RDYF : VREFINT ready flag
bits : 30 - 30 (1 bit)
access : read-only

REF_LOCK : REF_CTRL lock bit
bits : 31 - 31 (1 bit)
access : write-only


CFGR2

SYSCFG configuration register 2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR2 CFGR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FWDISEN CAPA I2C_PB6_FMP I2C_PB7_FMP I2C_PB8_FMP I2C_PB9_FMP I2C1_FMP I2C2_FMP

FWDISEN : Firewall disable bit
bits : 0 - 0 (1 bit)

CAPA : Configuration of internal VLCD rail connection to optional external capacitor
bits : 1 - 3 (3 bit)

I2C_PB6_FMP : Fm+ drive capability on PB6 enable bit
bits : 8 - 8 (1 bit)

I2C_PB7_FMP : Fm+ drive capability on PB7 enable bit
bits : 9 - 9 (1 bit)

I2C_PB8_FMP : Fm+ drive capability on PB8 enable bit
bits : 10 - 10 (1 bit)

I2C_PB9_FMP : Fm+ drive capability on PB9 enable bit
bits : 11 - 11 (1 bit)

I2C1_FMP : I2C1 Fm+ drive capability enable bit
bits : 12 - 12 (1 bit)

I2C2_FMP : I2C2 Fm+ drive capability enable bit
bits : 13 - 13 (1 bit)


EXTICR1

external interrupt configuration register 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTICR1 EXTICR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI0 EXTI1 EXTI2 EXTI3

EXTI0 : EXTI x configuration (x = 0 to 3)
bits : 0 - 3 (4 bit)

EXTI1 : EXTI x configuration (x = 0 to 3)
bits : 4 - 7 (4 bit)

EXTI2 : EXTI x configuration (x = 0 to 3)
bits : 8 - 11 (4 bit)

EXTI3 : EXTI x configuration (x = 0 to 3)
bits : 12 - 15 (4 bit)


EXTICR2

external interrupt configuration register 2
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTICR2 EXTICR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI4 EXTI5 EXTI6 EXTI7

EXTI4 : EXTI x configuration (x = 4 to 7)
bits : 0 - 3 (4 bit)

EXTI5 : EXTI x configuration (x = 4 to 7)
bits : 4 - 7 (4 bit)

EXTI6 : EXTI x configuration (x = 4 to 7)
bits : 8 - 11 (4 bit)

EXTI7 : EXTI x configuration (x = 4 to 7)
bits : 12 - 15 (4 bit)



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