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ACMP

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x30 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR0

CR4

DR

SR

FD

OPA

OPB

OPC

DACSR

CR1

CR2

CR3


CR0

ACMP0 Configuration Register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR0 CR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MOD OPE IE HYST EN

MOD : ACMP0 sensitivity modes of the interrupt trigger
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 00

ACMP0 interrupt on output falling edge.

#01 : 01

ACMP0 interrupt on output rising edge.

#10 : 10

ACMP0 interrupt on output falling edge.

#11 : 11

ACMP0 interrupt on output falling or rising edge.

End of enumeration elements list.

OPE : ACMP0 hall output Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

ACMP0 hall output Disabled.

#1 : 1

ACMP0 hall output enabled.

End of enumeration elements list.

IE : ACMP0 Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the ACMP Interrupt.

#1 : 1

Enable the ACMP Interrupt.

End of enumeration elements list.

HYST : Analog Comparator Hysterisis Selection
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

20 mV.

#1 : 1

30 mV.

End of enumeration elements list.

EN : Analog Comparator Enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

The ACMP is disabled.

#1 : 1

The ACMP is enabled.

End of enumeration elements list.


CR4

ACMP0 configuration register 4
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR4 CR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLSEQ

PLSEQ : ACMP0 polling channel sequence set
bits : 0 - 5 (6 bit)
access : read-write


DR

ACMP0 data output register 0
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DR DR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 O0 O1 O2 O3 O4 O5 O

O0 : ACMP0 polling mode channel 0 output
bits : 0 - 0 (1 bit)
access : read-write

O1 : ACMP0 polling mode channel 1 output
bits : 1 - 1 (1 bit)
access : read-write

O2 : ACMP0 polling mode channel 2 output
bits : 2 - 2 (1 bit)
access : read-write

O3 : ACMP0 polling mode channel 3 output
bits : 3 - 3 (1 bit)
access : read-write

O4 : ACMP0 polling mode channel 4 output
bits : 4 - 4 (1 bit)
access : read-write

O5 : ACMP0 polling mode channel 5 output
bits : 5 - 5 (1 bit)
access : read-write

O : ACMP0 normal mode output
bits : 7 - 7 (1 bit)
access : read-write


SR

ACMP0 status register 0
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SR SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F0 F1 F2 F3 F4 F5 WPF F

F0 : ACMP0 polling mode channel 0 interrupt flag
bits : 0 - 0 (1 bit)
access : read-write

F1 : ACMP0 polling mode channel 1 interrupt flag
bits : 1 - 1 (1 bit)
access : read-write

F2 : ACMP0 polling mode channel 2 interrupt flag
bits : 2 - 2 (1 bit)
access : read-write

F3 : ACMP0 polling mode channel 3 interrupt flag
bits : 3 - 3 (1 bit)
access : read-write

F4 : ACMP0 polling mode channel 4 interrupt flag
bits : 4 - 4 (1 bit)
access : read-write

F5 : ACMP0 polling mode channel 5 interrupt flag
bits : 5 - 5 (1 bit)
access : read-write

WPF : ACMP0 low power mode wakeup interrupt flag
bits : 6 - 6 (1 bit)
access : read-write

F : ACMP0 normal mode interrupt flag
bits : 7 - 7 (1 bit)
access : read-write


FD

ACMP0 polling frequency divider register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FD FD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLFD

PLFD : ACMP0 polling mode frequency divider
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 00

source_clk/256

#01 : 01

source_clk/100

#10 : 10

source_clk/70

#11 : 11

source_clk/50

End of enumeration elements list.


OPA

ACMP0 hall output A set register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPA OPA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OPASEL

OPASEL : ACMP0 Hall output A set
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#000 : 000

polling channel 0

#001 : 001

polling channel 1

#010 : 010

polling channel 2

#011 : 011

polling channel 3

#100 : 100

polling channel 4

#101 : 101

polling channel 5

#110 : 110

ACMP0 output tie 0

#111 : 111

ACMP0 output tie 0

End of enumeration elements list.


OPB

ACMP0 hall output B set register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPB OPB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OPBSEL

OPBSEL : ACMP0 Hall output B set
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#000 : 000

polling channel 0

#001 : 001

polling channel 1

#010 : 010

polling channel 2

#011 : 011

polling channel 3

#100 : 100

polling channel 4

#101 : 101

polling channel 5

#110 : 110

ACMP0 output tie 0

#111 : 111

ACMP0 output tie 0

End of enumeration elements list.


OPC

ACMP0 hall output C set register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPC OPC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OPCSEL

OPCSEL : ACMP0 Hall output C set
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#000 : 000

polling channel 0

#001 : 001

polling channel 1

#010 : 010

polling channel 2

#011 : 011

polling channel 3

#100 : 100

polling channel 4

#101 : 101

polling channel 5

#110 : 110

ACMP0 output tie 0

#111 : 111

ACMP0 output tie 0

End of enumeration elements list.


DACSR

ACMP DAC reference select register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DACSR DACSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACREF

DACREF : ACMP DAC reference select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

DAC selects bandgap as reference

#1 : 1

DAC selects Vdd as reference

End of enumeration elements list.


CR1

ACMP Configuration Register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR1 CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NSEL PSEL

NSEL : ACMP0 Negative Input Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#000 : 000

External input 0

#001 : 001

External input 1

#010 : 010

External input 2

#011 : 011

External input 3

#100 : 100

External input 4

#101 : 101

DAC0 Output

#110 : 110

ACMP0 output tie 0

#111 : 111

ACMP0 output tie 0

End of enumeration elements list.

PSEL : ACMP0 Positive Input Select
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

#000 : 000

External input 0

#001 : 001

External input 1

#010 : 010

External input 2

#011 : 011

External input 3

#100 : 100

External input 4

#101 : 101

DAC0 Output

#110 : 110

ACMP0 output tie 0

#111 : 111

ACMP0 output tie 0

End of enumeration elements list.


CR2

ACMP0 configuration register 2
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR2 CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VAL DACEN

VAL : DAC0 Output Level Selection
bits : 0 - 5 (6 bit)
access : read-write

DACEN : DAC Enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

The DAC0 is disabled.

#1 : 1

The DAC0 is enabled.

End of enumeration elements list.


CR3

ACMP0 configuration register 3
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR3 CR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NSPLEN PSPLEN

NSPLEN : ACMP0 negative input polling mode enable
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

ACMP0 negative input polling mode disabled

#1 : 1

ACMP0 negative input polling mode enabled

End of enumeration elements list.

PSPLEN : ACMP0 positive input polling mode enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

ACMP0 positive input polling mode disabled

#1 : 1

ACMP0 positive input polling mode enabled

End of enumeration elements list.



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